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| STM8S105xx Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, UART, SPI, IC Interrupt management Nested interrupt controller with 32 interrupts * * Up to 37 external interrupts on 6 vectors LQFP48 7x7 LQFP44 10x10 LQFP32 7x7 Timers 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM) * * Advanced 3control timer: 16-bit, 4 CAPCOM channels, complementary outputs, dead-time insertion and flexible synchronization VFQFPN32 5x5 UFQFPN32 5x5 SDIP32 400 ml Features Core 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline * 8-bit basic timer with 8-bit prescaler * Auto wake-up timer * Window and independent watchdog timers Communications interfaces UART with clock output for synchronous operation, Smartcard, IrDA, LIN * * Extended instruction set * - Memories Medium-density Flash/EEPROM: Program memory up to 32 Kbytes; data retention 20 years at 55C after 10 kcycles Data memory up to 1 Kbytes true data EEPROM; endurance 300 kcycles * * SPI interface up to 8 Mbit/s * I C interface up to 400 Kbit/s 2 Analog-to-digital converter (ADC) 10-bit, 1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog * * RAM: Up to 2 Kbytes Clock, reset and supply management 2.95 V to 5.5 V operating voltage I/Os Up to 38 I/Os on a 48-pin package including 16 high sink outputs * clock 4 master * Flexible powercontrol, resonator clock sources: Low crystal oscillator - External clock input - Internal, user-trimmable 16 MHz RC - Internal low power 128 kHz RC * Clock security system with clock monitor * Power management: (wait, active-halt, halt) - Low power modes - Switch-off peripheral clocks individually * Permanently active, low consumption power-on and power-down reset April 2010 * * Highly robust I/O design, immune against current injection Development support Embedded single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging * * Unique ID 96-bit unique key for each device Table 1: Device summary Reference Part number STM8S105xx STM8S105K4, STM8S105K6, STM8S105S4, STM8S105S6, STM8S105C4, STM8S105C6 DocID14771 Rev 9 1/127 www.st.com Contents STM8S105xx Contents 1 2 3 4 Introduction ..............................................................................................................8 Description ...............................................................................................................9 Block diagram ........................................................................................................11 Product overview ...................................................................................................12 4.1 Central processing unit STM8 .....................................................................................12 4.2 Single wire interface module (SWIM) and debug module (DM) ..................................12 4.3 Interrupt controller .......................................................................................................13 4.4 Flash program and data EEPROM memory ................................................................13 4.5 Clock controller ............................................................................................................14 4.6 Power management ....................................................................................................15 4.7 Watchdog timers ..........................................................................................................16 4.8 Auto wakeup counter ...................................................................................................16 4.9 Beeper ........................................................................................................................16 4.10 TIM1 - 16-bit advanced control timer .........................................................................17 4.11 TIM2, TIM3 - 16-bit general purpose timers ..............................................................17 4.12 TIM4 - 8-bit basic timer ..............................................................................................17 4.13 Analog-to-digital converter (ADC1) ............................................................................18 4.14 Communication interfaces .........................................................................................18 4.14.1 UART2 ...............................................................................................18 4.14.2 SPI .....................................................................................................19 4.14.3 IC ......................................................................................................19 5 Pinout and pin description ...................................................................................21 5.1 STM8S105 pinouts and pin description .......................................................................22 5.1.1 Alternate function remapping ...............................................................28 6 Memory and register map .....................................................................................29 6.1 Memory map 6.2 Register map 6.2.1 6.2.2 6.2.3 ................................................................................................................29 ...............................................................................................................30 I/O port hardware register map ............................................................30 General hardware register map ...........................................................33 CPU/SWIM/debug module/interrupt controller registers ......................47 7 Interrupt vector mapping ......................................................................................50 8 Option bytes ...........................................................................................................52 9 Unique ID ................................................................................................................57 10 Electrical characteristics ....................................................................................58 10.1 Parameter conditions .................................................................................................58 10.1.1 Minimum and maximum values .........................................................58 10.1.2 Typical values .....................................................................................58 2/127 DocID14771 Rev 9 STM8S105xx Contents 10.1.3 Typical curves ....................................................................................58 10.1.4 Typical current consumption ..............................................................58 10.1.5 Loading capacitor ...............................................................................59 10.1.6 Pin input voltage .................................................................................59 10.2 Absolute maximum ratings ........................................................................................59 10.3 Operating conditions ..................................................................................................61 10.3.1 VCAP external capacitor ....................................................................64 10.3.2 Supply current characteristics ............................................................64 10.3.3 External clock sources and timing characteristics .............................76 10.3.4 Internal clock sources and timing characteristics ...............................78 10.3.5 Memory characteristics ......................................................................81 10.3.6 I/O port pin characteristics .................................................................82 10.3.7 Typical output level curves .................................................................86 10.3.8 Reset pin characteristics ....................................................................91 10.3.9 SPI serial peripheral interface ............................................................93 2 10.3.10 I C interface characteristics .............................................................97 10.3.11 10-bit ADC characteristics ................................................................98 10.3.12 EMC characteristics .......................................................................102 11 Package characteristics ....................................................................................106 11.1 Ecopack packages ..................................................................................................106 11.2 Package mechanical data ........................................................................................106 11.2.1 48-pin LQFP package mechanical data ...........................................106 11.2.2 44-pin LQFP package mechanical data ...........................................108 11.2.3 32-pin LQFP package mechanical data ...........................................109 11.2.4 32-lead VFQFPN package mechanical data ....................................111 11.2.5 32-lead UFQFPN package mechanical data ....................................112 11.2.6 SDIP32 package mechanical data ...................................................114 11.3 Thermal characteristics ............................................................................................115 11.3.1 Reference document ........................................................................116 11.3.2 Selecting the product temperature range .........................................116 12 Ordering information .........................................................................................117 12.1 STM8S105 FASTROM microcontroller option list ...................................................117 13 STM8 development tools ..................................................................................122 13.1 Emulation and in-circuit debugging tools .................................................................122 13.2 Software tools ..........................................................................................................122 13.2.1 STM8 toolset ....................................................................................123 13.2.2 C and assembly toolchains ..............................................................123 13.3 Programming tools ..................................................................................................123 14 Revision history .................................................................................................124 DocID14771 Rev 9 3/127 List of tables STM8S105xx List of tables Table 1. Device summary .........................................................................................................................1 Table 2. STM8S105xx access line features .............................................................................................9 Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................15 Table 4. TIM timer features ...................................................................................................................17 Table 5. Legend/abbreviations ..............................................................................................................21 Table 6. Pin description for STM8S105 microcontrollers .......................................................................25 Table 7. Flash, Data EEPROM and RAM boundary addresses ..........................................................108 Table 8. I/O port hardware register map ..............................................................................................113 Table 9. General hardware register map ................................................................................................33 Table 10. CPU/SWIM/debug module/interrupt controller registers ......................................................114 Table 11. Interrupt mapping ....................................................................................................................50 Table 12. Option bytes ..........................................................................................................................57 Table 13. Option byte description ...........................................................................................................53 Table 14. Description of alternate function remapping bits [7:0] of OPT2 ..............................................55 Table 15. Unique ID registers (96 bits) ...................................................................................................57 Table 16. Voltage characteristics ...........................................................................................................59 Table 17. Current characteristics ...........................................................................................................60 Table 18. Thermal characteristics ..........................................................................................................61 Table 19. General operating conditions .................................................................................................62 Table 20. Operating conditions at power-up/power-down ......................................................................63 Table 21. Total current consumption with code execution in run mode at VDD = 5 V .............................64 Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................76 Table 23. Total current consumption in wait mode at VDD = 5 V ............................................................67 Table 24. Total current consumption in wait mode at VDD = 3.3 V .........................................................68 Table 25. Total current consumption in active halt mode at VDD = 5 V ..................................................68 Table 26. Total current consumption in active halt mode at VDD = 3.3 V ...............................................69 Table 27. Total current consumption in halt mode at VDD = 5 V .............................................................70 Table 28. Total current consumption in halt mode at VDD = 3.3 V ..........................................................71 Table 29. Wakeup times .........................................................................................................................71 Table 30. Total current consumption and timing in forced reset state ..................................................104 Table 31. Peripheral current consumption .............................................................................................72 Table 32. HSE user external clock characteristics .................................................................................76 Table 33. HSE oscillator characteristics .................................................................................................77 Table 34. HSI oscillator characteristics ..................................................................................................78 Table 35. LSI oscillator characteristics ...................................................................................................80 Table 36. RAM and hardware registers ..................................................................................................81 Table 37. Flash program memory/data EEPROM memory ....................................................................81 Table 38. I/O static characteristics .........................................................................................................82 Table 39. Output driving current (standard ports) ..................................................................................84 Table 40. Output driving current (true open drain ports) ........................................................................85 Table 41. Output driving current (high sink ports) ..................................................................................85 Table 42. NRST pin characteristics ........................................................................................................91 Table 43. SPI characteristics ..................................................................................................................94 2 Table 44. I C characteristics ..................................................................................................................97 Table 45. ADC characteristics ................................................................................................................98 Table 46. ADC accuracy with RAIN < 10 k , VDDA= 5 V .......................................................................99 Table 47. ADC accuracy with RAIN < 10 k RAIN, VDDA = 3.3 V ..........................................................100 4/127 DocID14771 Rev 9 STM8S105xx List of tables Table 48. EMS data ..............................................................................................................................103 Table 49. EMI data ...............................................................................................................................103 Table 50. ESD absolute maximum ratings ...........................................................................................104 Table 51. Electrical sensitivities ...........................................................................................................104 Table 52. 48-pin low profile quad flat package mechanical data .........................................................106 Table 53. 44-pin low profile quad flat package mechanical data .........................................................108 Table 54. 32-pin low profile quad flat package mechanical data .........................................................124 Table 55. 32-lead very thin fine pitch quad flat no-lead package mechanical data ..............................113 Table 56. 32-lead ultra thin fine pitch quad flat no-lead package mechanical data .............................113 Table 57. 32-lead shrink plastic DIP (400 ml) package mechanical data ............................................114 (1) Table 58. Thermal characteristics ....................................................................................................115 Table 59. Document revision history ...................................................................................................124 DocID14771 Rev 9 5/127 List of figures STM8S105xx List of figures Figure 1. STM8S105xx access line block diagram ................................................................................11 Figure 2. Flash memory organisation ....................................................................................................14 Figure 3. LQFP 48-pin pinout .................................................................................................................22 Figure 4. LQFP 44-pin pinout .................................................................................................................23 Figure 5. LQFP/VFQFPN/UFQFPN 32-pin pinout ................................................................................24 Figure 6. SDIP 32-pin pinout ..................................................................................................................25 Figure 7. Memory map ...........................................................................................................................29 Figure 8. Supply current measurement conditions ................................................................................58 Figure 9. Pin loading conditions .............................................................................................................59 Figure 10. Pin input voltage ...................................................................................................................59 Figure 11. fCPUmax versus VDD ..............................................................................................................63 Figure 12. External capacitor CEXT .......................................................................................................64 Figure 13. Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz ...........................................73 Figure 14. Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V ..................................................74 Figure 15. Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz ..............................................................74 Figure 16. Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz ............................................75 Figure 17. Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V ....................................................75 Figure 18. Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz ................................................................76 Figure 19. HSE external clocksource .....................................................................................................77 Figure 20. HSE oscillator circuit diagram ...............................................................................................78 Figure 21. Typical HSI accuracy at VDD = 5 V vs 5 temperatures ..........................................................79 Figure 22. Typical HSI accuracy vs VDD @ 4 temperatures ..................................................................80 Figure 23. Typical LSI accuracy vs VDD @ 4 temperatures ...................................................................81 Figure 24. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................83 Figure 25. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................84 Figure 26. Typical pull-up current vs VDD @ 4 temperatures .................................................................84 Figure 27. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................86 Figure 28. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................87 Figure 29. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................87 Figure 30. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................88 Figure 31. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................88 Figure 32. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................89 Figure 33. Typ. VDD - VOH @ VDD = 5 V (standard ports) .......................................................................89 Figure 34. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ....................................................................90 Figure 35. Typ. VDD - VOH @ VDD = 5 V (high sink ports) ......................................................................90 Figure 36. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) ...................................................................91 Figure 37. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................92 Figure 38. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................92 Figure 39. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................93 Figure 40. Recommended reset pin protection ......................................................................................93 Figure 41. SPI timing diagram - slave mode and CPHA = 0 ..................................................................95 (1) Figure 42. SPI timing diagram - slave mode and CPHA = 1 .............................................................96 (1) Figure 43. SPI timing diagram - master mode ...................................................................................96 2 (1) Figure 44. Typical application with I C bus and timing diagram .......................................................98 Figure 45. ADC accuracy characteristics .............................................................................................101 Figure 46. Typical application with ADC ..............................................................................................102 Figure 47. 48-pin low profile quad flat package (7 x 7) ........................................................................106 6/127 DocID14771 Rev 9 STM8S105xx List of figures Figure 48. 44-pin low profile quad flat package ...................................................................................108 Figure 49. 32-pin low profile quad flat package (7 x 7) ........................................................................109 Figure 50. 32-lead very thin fine pitch quad flat no-lead package (5 x 5) ............................................112 Figure 51. 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5) ............................................112 Figure 52. 32-lead shrink plastic DIP (400 ml) package ......................................................................114 Figure 53. STM8S105xx access line ordering information scheme .....................................................117 DocID14771 Rev 9 7/127 Introduction STM8S105xx 1 Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016). * on programming, erasing and of the internal * For informationthe STM8S Flash programmingprotection(PM0051). Flash memory please refer to manual debug and SWIM (single wire interface module) refer * For information on the protocol and debug module user manual (UM0470). to the STM8 SWIM communication * For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). 8/127 DocID14771 Rev 9 STM8S105xx Description 2 Description The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash program memory, plus integrated true data EEPROM. They are referred to as medium-density devices in the STM8S microcontroller family reference manual (RM0016). All devices of the STM8S105xx access line provide the following benefits: Reduced system cost Integrated true data EEPROM for up to 300 k write/erase cycles * - High system integration level with internal clock oscillators, watchdog and brown-out reset. robustness * Performance andclock frequency 16 MHz CPU - Robust I/O, independent watchdogs with separate clock source - Clock security system * Short development cycles across a common family product architecture with compatible - Applications scalability and modular peripherals. pinout, memory map and - Full documentation and a wide choice of development tools * Product longevity and peripherals made in a state-of-the art technology - Advanced core - A family of products for applications with 2.95 to 5.5 V operating supply Table 2: STM8S105xx access line features Device Pin count Maximum number of GPIOs Ext. Interrupt pins Timer CAPCOM channels Timer complementary outputs A/D Converter channels High sink I/Os Medium density Flash Program memory (bytes) Data EEPROM (bytes) RAM (bytes) STM8S105C6 48 38 STM8S105C4 48 38 STM8S105S6 44 34 STM8S105S4 44 34 STM8S105K6 32 25 STM8S105K4 32 25 35 9 35 9 31 8 31 8 23 8 23 8 3 3 3 3 3 3 10 10 9 9 7 7 16 32K 16 16K 15 32K 15 16K 12 32K 12 16K 1024 1024 1024 1024 1024 1024 2K 2K 2K 2K 2K 2K DocID14771 Rev 9 9/127 Description Device Peripheral set STM8S105C6 STM8S105C4 STM8S105S6 STM8S105S4 STM8S105K6 STM8S105xx STM8S105K4 2 Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I C, UART, Window WDG, Independent WDG, ADC 10/127 DocID14771 Rev 9 STM8S105xx Block diagram 3 Block diagram Figure 1: STM8S105xx access line block diagram Reset block Clock controller Reset Reset XTAL 1-16 MHz RC int. 16 MHz Detector POR BOR RC int. 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG Single wire debug interf. Master/slave autosynchro LIN master SPI emul. 400 Kbit/s Debug/SWIM Up to 32 Kbytes program Flash UART2 Address and data bus 1 Kbytes data EEPROM Up to 2 Kbytes RAM IC 2 8 Mbit/s SPI Boot ROM Up to 4 CAPCOM channels +3 complementary outputs Up to 5 CAPCOM channels 16-bit advanced control timer (TIM1) 16-bit general purpose timers (TIM2, TIM3) Up to 10 channels ADC1 8-bit basic timer (TIM4) 1/2/4 kHz beep Beeper AWU timer DocID14771 Rev 9 11/127 Product overview STM8S105xx 4 Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. Architecture and registers Harvard architecture * * 3-stage pipeline * 32-bit wide program memory bus - single cycle fetching for most instructions * X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations * 8-bit accumulator * 24-bit program counter - 16-Mbyte linear memory space * 16-bit stack pointer - access to a 64 K-level stack * 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing 20 addressing modes * * Indexed indirect addressing mode for look-up tables located anywhere in the address space * Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2-byte average instruction size * * Standard data movement and logic/arithmetic functions * 8-bit by 8-bit multiplication * 16-bit by 8-bit and 16-bit by 16-bit division * Bit manipulation * Data transfer between stack and accumulator (push/pop) with direct stack access * Data transfer using the X and Y registers or direct memory-to-memory transfers 4.2 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming. 12/127 DocID14771 Rev 9 STM8S105xx SWIM Product overview Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers. R/W to RAM and peripheral registers in real-time * * R/W access to all resources by stalling the CPU * Breakpoints on all program-memory instructions (software breakpoints) * Two advanced breakpoints, 23 predefined configurations 4.3 Interrupt controller * Nested interrupts with three software priority levels * 32 interrupt vectors with hardware priority * Up to 27 external interrupts on 6 vectors including TLI * Trap and reset interrupts 4.4 Flash program and data EEPROM memory * Up to 32 Kbytes of Flash program single voltage Flash memory * Up to 1 Kbytes true data EEPROM * Read while write: Writing in data memory possible while executing code in program memory * User option byte area Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below. The size of the UBC is programmable through the UBC option byte, in increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: Main program memory: Up to 32 Kbytes minus UBC * * User-specific boot code (UBC): Configurable up to 32 Kbytes DocID14771 Rev 9 13/127 Product overview STM8S105xx The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Figure 2: Flash memory organisation Data EEPROM memory Data memory area ( 1 Kbyte) Option bytes UBC area Remains write protected during IAP Programmable area from 1 Kbyte (2 first pages) up to 32 Kbytes (1 page steps) Medium density Flash program memory (up to 32 Kbytes) Program memory area Write access possible for IAP Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. 4.5 Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. * Clock in * Safe clock switching: register.sources can be changed safely on the flynewrun mode through a configuration The clock signal is not switched until the clock source is ready. The design guarantees glitch-free switching. consumption, * Clocktomanagement: To reduce poweror memory. the clock controller can stop the clock the core, individual peripherals * Master clock sources: Four different clock sources can be used to drive the master clock: - 1-16 MHz high-speed external crystal (HSE) - Up to 16 MHz high-speed user-external clock (HSE user-ext) 14/127 DocID14771 Rev 9 STM8S105xx Product overview - 16 MHz high-speed internal RC oscillator (HSI) 128 kHz low-speed internal RC (LSI) After reset, * Startup clock:The prescalerthe microcontroller restarts by default with an internal 2 MHz clock (HSI/8). ratio and clock source can be changed by the application program as soon as the code execution starts. system (CSS): This feature can be enabled by software. an * Clock securitythe internal RC (16 MHz/8) is automatically selected by theIfCSSHSE clock failure occurs, and an interrupt can optionally be generated. * Configurable main clock output (CCO): This outputs an external clock for use by the application. Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers Bit Peripheral Bit clock Peripheral Bit clock Peripheral Bit clock Peripheral clock PCKEN1 7 TIM1 PCKEN1 6 TIM3 PCKEN1 5 TIM2 PCKEN1 4 TIM4 PCKEN1 3 UART2 PCKEN1 2 Reserved PCKEN1 1 SPI PCKEN1 0 I C 2 PCKEN2 7 Reserved PCKEN2 6 Reserved PCKEN2 5 Reserved PCKEN2 4 Reserved PCKEN2 3 ADC PCKEN2 2 AWU PCKEN2 1 Reserved PCKEN2 0 Reserved 4.6 Power management For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. * mode, the CPU and peripheral clocks are * Active halt mode with regulator on: In thisprogrammable intervals by the auto wake up stopped. An internal wakeup is generated at unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. mode off: This same as halt with * Active haltthat thewith regulatorregulator ismode is theoff, so the active up time isregulator on, except main voltage powered wake slower. In this mode the and peripheral * Halt mode:stopped, the mainmicrocontroller uses the least power. The CPUtriggered by clocks are voltage regulator is powered off. Wakeup is external event or reset. DocID14771 Rev 9 15/127 Product overview STM8S105xx 4.7 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 s up to 64 ms. 2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register. Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 s to 1 s. 4.8 Auto wakeup counter * Used for auto wakeup from active halt mode * Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock * LSI clock can be internally connected to TIM3 input capture channel 1 for calibration 4.9 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. The beeper output port is only available through the alternate function remap option bit AFR7. 16/127 DocID14771 Rev 9 STM8S105xx Product overview 4.10 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver 16-bit up, down and up/down autoreload counter with 16-bit prescaler * (CAPCOM) as input capture, * Four independent capture/compare channelscenter alignedconfigurable single pulse mode output compare, PWM generation (edge and mode) and output * Synchronization module to control the timer with external signals * Break input to force the timer outputs into a defined state * Three complementary outputs with adjustable dead time * Encoder mode * Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break 4.11 TIM2, TIM3 - 16-bit general purpose timers * 16-bit autoreload (AR) up-counter * 15-bit prescaler adjustable to fixed power of 2 ratios 1...32768 * Timers with 3 or 2 individually configurable capture/compare channels * PWM mode * Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update 4.12 TIM4 - 8-bit basic timer * 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 * Clock source: CPU clock * Interrupt source: 1 x overflow/update Table 4: TIM timer features Timer Counter Prescaler size (bits) 16 Counting CAPCOM Complem. Ext. Timer mode channels outputs trigger synchronization/ chaining 4 3 Yes No TIM1 Any integer from 1 to Up/ 65536 down Any power of 2 from 1 to 32768 Any power of 2 from 1 to 32768 Up TIM2 16 3 0 No TIM3 16 Up 2 0 No DocID14771 Rev 9 17/127 Product overview STM8S105xx Timer Counter Prescaler size (bits) 8 Any power of 2 from 1 to 128 Counting CAPCOM Complem. Ext. Timer mode channels outputs trigger synchronization/ chaining Up 0 0 No TIM4 4.13 Analog-to-digital converter (ADC1) The STM8 family products contain a 10-bit successive approximation A/D converter (ADC1) with up to 5 external multiplexed input channels and the following main features: Input voltage range: 0 to VDD * * Conversion time: 14 clock cycles * Single and continuous and buffered continuous conversion modes * Buffer size (n x 10 bits) where n = number of input channels * Scan mode for single and continuous conversion of a sequence of channels * Analog watchdog capability with programmable upper and lower thresholds * Analog watchdog interrupt * External trigger input * Trigger from TIM1 TRGO * End of conversion (EOC) interrupt 4.14 Communication interfaces The following communication interfaces are implemented: UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, LIN2.1 master/slave capability * * SPI : Full and half-duplex, 8 Mbit/s * IC: Up to 400 Kbit/s 4.14.1 UART2 Main features One Mbit/s full duplex SCI * * SPI emulation * High precision baud rate generator * Smartcard emulation * IrDA SIR encoder decoder * LIN master mode * LIN slave mode 18/127 DocID14771 Rev 9 STM8S105xx Asynchronous communication (UART mode) Full duplex communication - NRZ standard format (mark/space) Product overview * and up to 1 * Programmable transmitbaud receive baud ratesthe inputMbit/s (f /16) and capable of following any standard rate regardless of frequency * Separate enable bits for transmitter and receiver receiver wakeup * TwoAddress bit (MSB) modes: - Idle line (interrupt) * Transmission error detection with interrupt generation * Parity control CPU Synchronous communication Full duplex synchronous transfers * * SPI master operation * 8-bit data communication * Maximum speed: 1 Mbit/s at 16 MHz (f * * Reception: Detects 11-bit break frame CPU/16) LIN master mode Emission: Generates 13-bit synch break frame LIN slave mode Autonomous header handling - one single interrupt per valid message header * * Automatic baud rate synchronization - maximum tolerated initial clock deviation 15 % * Synch delimiter checking * 11-bit LIN synch break detection - break detection always active * Parity check on the LIN identifier field * LIN error management * Hot plugging support 4.14.2 SPI * Maximum speed: 8 Mbit/s (f /2) both for master and slave * Full duplex synchronous transfers * Simplex synchronous transfers on two lines with a possible bidirectional data line * Master or slave operation - selectable by hardware or software * CRC calculation * 1 byte Tx and Rx buffer * Slave/master selection input pin MASTER 4.14.3 IC master features: * IC Clock generation DocID14771 Rev 9 19/127 Product overview STM8S105xx Start and stop generation - slave features: * IC Programmable I2C address detection - Stop bit detection * Generation and detection of 7-bit/10-bit addressing and general call * Supports different communication speeds: - Standard speed (up to 100 kHz) - Fast speed (up to 400 kHz) 20/127 DocID14771 Rev 9 STM8S105xx Pinout and pin description 5 Pinout and pin description Table 5: Legend/abbreviations Type Level I= Input, O = Output, S = Power supply Input Output Output speed CM = CMOS HS = High sink O1 = Slow (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset Port and control configuration Input Output Bold X High sink capability. float = floating, wpu = weak pull-up T = True open drain, OD = Open drain, PP = Push pull Reset state HS (T) [] True open drain (P-buffer and protection diode to VDD not implemented Alternate function remapping option DocID14771 Rev 9 21/127 Pinout and pin description STM8S105xx 5.1 STM8S105 pinouts and pin description Figure 3: LQFP 48-pin pinout PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PD7/TLI [TIM1_CH4] PD6/UART2_RX PD5/UART2_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] NRST OSCIN/PA1 OSCOUT/PA2 V SSIO_1 VSS VCAP VDD 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PE0 (HS)/CLK_CCO 2 PE1 (T)/I C_SCL 2 PE2 (T)/I C_SDA PE3/TIM1_BKIN PG1 PG0 VDDIO_1 [TIM3_CH1] TIM2_CH3/PA3 (HS) PA4 (HS) PA5 (HS) PA6 PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1/UART2_CK PE5/SPI_NSS 13 14 15 16 17 18 19 20 21 22 23 24 AIN6/PB6 2 [I C_SDA] AIN5/PB5 2 [I C_SCL] AIN4/PB4 [TIM1_ETR/AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 VDDA VSSA AIN7/PB7 AIN8/PE7 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 22/127 DocID14771 Rev 9 AIN9/PE6 STM8S105xx Figure 4: LQFP 44-pin pinout Pinout and pin description PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PD7/TLI [TIM1_CH4] PD6/UART2_RX PD5/UART2_TX PD4 (HS)/TIM2_CH1[BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD 1 2 3 4 5 6 7 8 9 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA PG1 PG0 PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PD1 (HS)/SWIM VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1/UART2_CK PE5/SPI_NSS VDDIO_1 (HS) PA4 (HS) PA5 (HS) PA6 10 11 23 12 13 14 15 16 17 18 19 20 21 22 VSSA AIN6/PB6 [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 VDDA [TIM1_ETR] AIN3/PB3 AIN7/PB7 [TIM1_CH3N] AIN2/PB2 (T IM1_CH1N] AIN0/PB0 [TIM1_CH2N] AIN1/PB1 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). DocID14771 Rev 9 AIN9/PE6 23/127 Pinout and pin description Figure 5: LQFP/VFQFPN/UFQFPN 32-pin pinout STM8S105xx 32 31 30 29 28 27 26 25 NRST OSCIN/PA1 OSCOUT/PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 V DDA 24 23 22 21 20 19 18 17 PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 V SS VCAP V DD V DDIO AIN12/PF4 PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1[TIM2_CH3] PD4 (HS)/TIM2_CH1 [BEEP] PD7/TLI [TIM1_CH4] PD6/UART2_RX PD5/UART2_TX PD1 (HS)/SWIM PC1 (HS)/TIM1_CH1/UART2_CK PE5/SPI_NSS VSSA 2 [I C_SDA] AIN5/PB5 [TIM1_ETR] AIN3/PB3 [TIM1_CH3N] AIN2/PB2 2 [I C_SCL] AIN4/PB4 [TIM1_CH2N] AIN1/PB1 1. (HS) high sink capability. 2. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 24/127 DocID14771 Rev 9 [TIM1_CH1N] AIN0/PB0 STM8S105xx Figure 6: SDIP 32-pin pinout Pinout and pin description ADC_ETR/TIM2_CH2/PD3(HS) [BEEP]TIM2_CH1/PD4(HS) UART2_TX/PD5 UART2_RX/PD6 (TIM1_CH4)TLI/PD7 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD VDDIO AIN12/PF4 VDDA VSSA [I2C_SDA]AIN5/PB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PD2(HS)/TIM3_CH1[TIM2_CH3] PD1(HS)/SWIM PD0(HS)/TIM3_CH2[TIM1_BKIN][CLK_CCO] PC7(HS)/SPI_MISO PC6(HS)/SPI_MOSI PC5(HS)/SPI_SCK PC4(HS)/TIM1_CH4 PC3(HS)/TIM1_CH3 PC2(HS)/TIM1_CH2 PC1(HS)/TIM1_CH1/UART2_CK PE5/SPI_NSS PB0/AIN0[TIM1_CH1N] PB1/AIN1[TIM1_CH2N] PB2/AIN2[TIM1_CH3N] PB3/AIN3[TIM1_ETR] PB4/AIN4[I2C_SCL] 105_ai15057 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode to VDD not implemented). 3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). Table 6: Pin description for STM8S105 microcontrollers Pin number LQFP48 LQFP44 LQFP32/ VFQFPN32/ UFQFPN32 SDIP32 Pin name Type Input floating wpu Output Ext. High interrupt sink Speed OD PP Main function (after reset) Default alternate function Alternate function after remap [option bit] 1 1 1 6 NRST I/O X Reset 2 2 2 7 PA1/ OSC IN I/O X X O1 X X Port A1 Resonator/ crystal in 3 3 3 8 PA2/ OSC OUT I/O X X X O1 X X Port A2 Resonator/ crystal out 4 4 - - VSSIO_1 S I/O ground 5 5 4 9 VSS S Digital ground 6 6 5 10 VCAP S 1.8 V regulator capacitor 7 7 6 11 VDD S Digital power supply 8 8 7 12 VDDIO_1 S I/O power supply DocID14771 Rev 9 25/127 Pinout and pin description STM8S105xx Pin number LQFP48 LQFP44 LQFP32/ VFQFPN32/ UFQFPN32 SDIP32 Pin name Type Input floating wpu Output Ext. High interrupt sink Speed OD PP Main function (after reset) Default alternate function Alternate function after remap [option bit] 9 - - - PA3/ TIM2 _CH3 [TIM3 _CH1] I/O X X X O1 X X Port A3 Timer 2 channel 3 TIM3_ CH1 [AFR1] 10 9 - - PA4 I/O X X X HS O3 X X Port A4 11 10 - - PA5 I/O X X X HS O3 X X Port A5 12 11 - - PA6 I/O X X X HS O3 X X Port A6 (1) Analog input 12 - - 8 13 PF4/ AIN12 I/O X X O1 X X Port F4 13 12 9 14 VDDA S Analog power supply 14 13 10 15 VSSA S Analog ground 15 14 - - PB7/ AIN7 I/O X X X O1 X X Port B7 Analog input 7 16 15 - - PB6/ AIN6 I/O X X X O1 X X Port B6 Analog input 6 17 16 11 16 PB5/ AIN5 2 [I C_ SDA] I/O X X X O1 X X Port B5 Analog input 5 2 I C_SDA [AFR6] 18 17 12 17 PB4/ AIN4 2 [I C_ SCL] I/O X X X O1 X X Port B4 Analog input 4 2 I C_SCL [AFR6] 19 18 13 18 PB3/ AIN3 [TIM1_ ETR] I/O X X X O1 X X Port B3 Analog input 3 TIM1_ ETR [AFR5] 20 19 14 19 PB2/ AIN2 [TIM1_ CH3N] I/O X X X O1 X X Port B2 Analog input 2 TIM1_ CH3N [AFR5] 21 20 15 20 PB1/ AIN1 [TIM1_ CH2N] I/O X X X O1 X X Port B1 Analog input 1 TIM1_ CH2N [AFR5] 22 21 16 21 PB0/ AIN0 [TIM1_ CH1N] I/O X X X O1 X X Port B0 Analog input 0 TIM1_ CH1N [AFR5] 23 - - - PE7/ AIN8 I/O X X X O1 X X Port E7 Analog input 8 26/127 DocID14771 Rev 9 STM8S105xx Pinout and pin description Pin number LQFP48 LQFP44 LQFP32/ VFQFPN32/ UFQFPN32 SDIP32 Pin name Type Input floating wpu Output Ext. High interrupt sink Speed OD PP Main function (after reset) Default alternate function Alternate function after remap [option bit] 24 22 - - PE6/ AIN9 I/O X X X O1 X X Port E6 (2) Analog input 9 25 23 17 22 PE5/SPI_ NSS I/O X X X O1 X X Port E5 SPI master/slave select 26 24 18 23 PC1/ TIM1_ CH1/ U R2C A T_ K I/O X X X HS O3 X X Port C1 Timer 1 channel 1/ UART2 synchronous clock 27 25 19 24 PC2/ TIM1_ CH2 I/O X X X HS O3 X X Port C2 Timer 1channel 2 28 26 20 25 PC3/ TIM1_ CH3 I/O X X X HS O3 X X Port C3 Timer 1 channel 3 29 - 21 26 PC4/ TIM1_ CH4 I/O X X X HS O3 X X Port C4 Timer 1 channel 4 30 27 22 27 PC5/ SPI_ SCK I/O X X X HS O3 X X Port C5 SPI clock 31 28 - - VSSIO_2 S I/O ground 32 29 - - VDDIO_2 S I/O power supply 33 30 23 28 PC6/ SPI_ MOSI I/O X X X HS O3 X X Port C6 SPI master out/slave in 34 31 24 29 PC7/ SPI_ MISO I/O X X X HS O3 X X Port C7 SPI master in/ slave out 35 32 - - PG0 I/O X X O1 X X Port G0 36 33 - - PG1 I/O X X O1 X X Port G1 37 - - - PE3/ TIM1_ BKIN I/O X X X O1 X X Port E3 Timer 1 - break input 38 34 - - PE2/ 2 I C_ SDA I/O X X X O1 (3) T Port E2 2 I C data 39 35 - - PE1/ 2 I C_ SCL I/O X X X O1 (3) T Port E1 2 I C clock 40 36 - - PE0/ CLK_ CCO I/O X X X HS O3 X X Port E0 Configurable clock output DocID14771 Rev 9 27/127 Pinout and pin description STM8S105xx Pin number LQFP48 LQFP44 LQFP32/ VFQFPN32/ UFQFPN32 SDIP32 Pin name Type Input floating wpu Output Ext. High interrupt sink Speed OD PP Main function (after reset) Default alternate function Alternate function after remap [option bit] 41 37 25 30 PD0/ TIM3_ CH2 [TIM1_ BKIN] [CLK_ CCO] I/O X X X HS O3 X X Port D0 Timer 3 channel 2 TIM1_ BKIN [AFR3]/ CLK_ CCO [AFR2] 42 38 26 31 PD1/ SWIM I/O X X X HS O4 X X Port D1 SWIM data interface 43 39 27 32 PD2/ TIM3_ CH1 [TIM2_ CH3] I/O X X X HS O3 X X Port D2 Timer 3 channel 1 TIM2_CH3 [AFR1] 44 40 28 1 PD3/ TIM2_ CH2 [ADC_ ETR] I/O X X X HS O3 X X Port D3 Timer 2 channel 2 ADC_ ETR [AFR0] 45 41 29 2 PD4/ TIM2_ CH1 [BEEP] I/O X X X HS O3 X X Port D4 Timer 2 channel 1 BEEP output [AFR7] 46 42 30 3 PD5/ UART2_ TX I/O X X X O1 X X Port D5 UART2 data transmit 47 43 31 4 PD6/ UART2_ RX I/O X X X O1 X X Port D6 UART2 data receive 48 44 32 5 PD7/ TLI [TIM1_ CH4] I/O X X X O1 X X Port D7 Top level interrupt TIM1_ CH4 [AFR4] (1) (2) (3) AIN12 is not selectable in ADC scan mode or with analog watchdog. In 44-pin package, AIN9 cannot be used by ADC scan mode. In the open-drain output column, `T' defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented). 5.1.1 Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016). 28/127 DocID14771 Rev 9 STM8S105xx Memory and register map 6 6.1 Memory and register map Memory map Figure 7: Memory map 0x00 0000 RAM (2 Kbytes) 0x00 07FF 512 bytes stack Reserved 0x00 4000 0x00 43FF 0x00 4400 0x00 47FF 0x00 4800 0x00 487F 0x00 4900 1 Kbyte data EEPROM Reserved Option bytes Reserved 0x00 4FFF 0x00 5000 GPIO and periph. reg. 0x00 57FF 0x00 5800 Reserved 0x00 5FFF 0x00 6000 2 Kbytes boot ROM 0x00 67FF 0x00 6800 Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F CPU/SWIM/debug/ITC registers 32 interrupt vectors Flash program memory (16 to 32 Kbytes) 0x00 FFFF 0x01 0000 Reserved 0x02 7FFF The following table lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. DocID14771 Rev 9 29/127 Memory and register map STM8S105xx Table 7: Flash, Data EEPROM and RAM boundary addresses Memory area Size (bytes) Start address 0x00 8000 0x00 8000 0x00 0000 0x00 4000 End address 0x00 FFFF 0x00 BFFF 0x00 07FF 0x00 43FF Flash program memory 32K 16K RAM Data EEPROM 2K 1024 6.2 6.2.1 Register map I/O port hardware register map Table 8: I/O port hardware register map Address Block Register label Register name Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 5000 Port A 0x00 5001 0x00 5002 0x00 5003 0x00 5004 0x00 5005 Port B 0x00 5006 0x00 5007 0x00 5008 0x00 5009 PA_ODR PA_IDR PA_DDR PA_CR1 PA_CR2 PB_ODR PB_IDR PB_DDR PB_CR1 PB_CR2 Port A data output latch register Port A input pin value register Port A data direction register Port A control register 1 Port A control register 2 Port B data output latch register Port B input pin value register Port B data direction register Port B control register 1 Port B control register 2 30/127 DocID14771 Rev 9 STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 500A Port C 0x00 500B 0x00 500C 0x00 500D 0x00 500E 0x00 500F Port D 0x00 5010 0x00 5011 0x00 5012 0x00 5013 0x00 5014 Port E 0x00 5015 0x00 5016 0x00 5017 0x00 5018 0x00 5019 Port F 0x00 501A 0x00 501B 0x00 501C PC_ODR PB_IDR PC_DDR PC_CR1 PC_CR2 PD_ODR PD_IDR PD_DDR PD_CR1 PD_CR2 PE_ODR PE_IDR PE_DDR PE_CR1 PE_CR2 PF_ODR PF_IDR PF_DDR PF_CR1 Port C data output latch register Port C input pin value register Port C data direction register Port C control register 1 Port C control register 2 Port D data output latch register Port D input pin value register Port D data direction register Port D control register 1 Port D control register 2 Port E data output latch register Port E input pin value register Port E data direction register Port E control register 1 Port E control register 2 Port F data output latch register Port F input pin value register Port F data direction register Port F control register 1 DocID14771 Rev 9 31/127 Memory and register map STM8S105xx Address Block Register label Register name Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 501D 0x00 501E Port G 0x00 501F 0x00 5020 0x00 5021 0x00 5022 0x00 5023 Port H 0x00 5024 0x00 5025 0x00 5026 0x00 5027 0x00 5028 Port I 0x00 5029 0x00 502A 0x00 502B 0x00 502C PF_CR2 PG_ODR PG_IDR PG_DDR PG_CR1 PG_CR2 PH_ODR PH_IDR PH_DDR PH_CR1 PH_CR2 PI_ODR PI_IDR PI_DDR PI_CR1 PI_CR2 Port F control register 2 Port G data output latch register Port G input pin value register Port G data direction register Port G control register 1 Port G control register 2 Port H data output latch register Port H input pin value register Port H data direction register Port H control register 1 Port H control register 2 Port I data output latch register Port I input pin value register Port I data direction register Port I control register 1 Port I control register 2 32/127 DocID14771 Rev 9 STM8S105xx Memory and register map 6.2.2 General hardware register map Table 9: General hardware register map Address Block Register label Register name Reset status 0x00 5050 to 0x00 5059 0x00 505A 0x00 505B 0x00 505C Reserved area (10 bytes) Flash FLASH_CR1 Flash control register 1 0x00 FLASH_CR2 Flash control register 2 0x00 FLASH_NCR2 Flash complementary control register 2 0xFF 0x00 505D 0x00 505E 0x00 505F 0x00 5060 to 0x00 5061 0x00 5062 0x00 5063 0x00 5064 FLASH _FPR Flash protection register 0x00 FLASH _NFPR Flash complementary protection register Flash in-application programming status register 0xFF FLASH _IAPSR 0x00 Reserved area (2 bytes) Flash FLASH _PUKR Flash program memory unprotection register 0x00 Reserved area (1 byte) Flash FLASH _DUKR Data EEPROM unprotection register 0x00 DocID14771 Rev 9 33/127 Memory and register map STM8S105xx Address Block Register label Register name Reset status 0x00 5065 to 0x00 509F 0x00 50A0 0x00 50A1 0x00 50A2 to 0x00 50B2 0x00 50B3 0x00 50B4 to 0x00 50BF 0x00 50C0 0x00 50C1 0x00 50C2 0x00 50C3 0x00 50C4 0x00 50C5 Reserved area (59 bytes) ITC EXTI EXTI_CR1 External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 Reserved area (17 bytes) RST RST_SR Reset status register xx Reserved area (12 bytes) CLK CLK_ICKR Internal clock control register 0x01 CLK_ECKR External clock control register 0x00 Reserved area (1 byte) CLK CLK_CMSR Clock master status register 0xE1 CLK_SWR Clock master switch register 0xE1 CLK_SWCR Clock switch control register 0bxxxx 0000 34/127 DocID14771 Rev 9 STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x18 0x00 50C6 0x00 50C7 0x00 50C8 0x00 50C9 0x00 50CA 0x00 50CB 0x00 50CC 0x00 50CD 0x00 50CE to 0x00 50D0 0x00 50D1 0x00 50D2 0x00 50D3 to 0x00 50DF CLK_CKDIVR Clock divider register CLK_PCKENR1 Peripheral clock gating register 1 0xFF CLK_CSSR Clock security system register 0x00 CLK_CCOR Configurable clock control register 0x00 CLK_PCKENR2 Peripheral clock gating register 2 0xFF CLK_CANCCR CAN clock control register 0x00 CLK_HSITRIMR HSI clock calibration trimming register xx CLK_SWIMCCR SWIM clock control register x0 Reserved area (3 bytes) WWDG WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F Reserved area (13 bytes) DocID14771 Rev 9 35/127 Memory and register map STM8S105xx Address Block Register label Register name Reset status - 0x00 50E0 0x00 50E1 0x00 50E2 0x00 50E3 to 0x00 50EF 0x00 50F0 0x00 50F1 0x00 50F2 0x00 50F3 0x00 50F4 to 0x00 50FF IWDG IWDG_KR IWDG key register IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF Reserved area (13 bytes) AWU AWU_CSR1 AWU control/ status register 1 0x00 AWU_APR AWU asynchronous prescaler buffer register AWU timebase selection register 0x3F AWU_TBR 0x00 BEEP BEEP_CSR BEEP control/ status register 0x1F Reserved area (12 bytes) 00 5200h SPI 00 5201h 00 5202h 00 5203h 00 5204h SPI_CR1 SPI_CR2 SPI_ICR SPI_SR SPI_DR SPI control register 1 SPI control register 2 SPI interrupt control register SPI status register SPI data register 0x00 0x00 0x00 0x02 0x00 36/127 DocID14771 Rev 9 STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x07 0xFF 0xFF 00 5205h 00 5206h 00 5207h SPI_CRCPR SPI_RXCRCR SPI_TXCRCR SPI CRC polynomial register SPI Rx CRC register SPI Tx CRC register 00 5208h Reserved area (8 bytes) to 00 520Fh 00 5210h I C 00 5211h 00 5212h 00 5213h 00 5214h 00 5215h 00 5216h 00 5217h 00 5218h 00 5219h 00 521Ah 00 521Bh 00 521Ch 00 521Dh 2 I2C_CR1 I2C_CR2 I2C_FREQR I2C_OARL I2C_OARH Reserved I2C_DR I2C_SR1 I2C_SR2 I2C_SR3 I2C_ITR I2C_CCRL I2C_CCRH I2C_TRISER I C control register 1 I C control register 2 I C frequency register I C Own address register low I C own address register high 2 2 2 2 2 0x00 0x00 0x00 0x00 0x00 I C data register I C status register 1 I C status register 2 I C status register 3 I C interrupt control register I C clock control register low I C clock control register high I C TRISE register 2 2 2 2 2 2 2 2 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 DocID14771 Rev 9 37/127 Memory and register map STM8S105xx Address Block Register label Register name Reset status 0x00 00 521Eh I2C_PECR I C packet error checking register 2 00 521Fh Reserved area (17 bytes) to 00 522Fh 0x00 5230 to 0x00 523F 0x00 5240 0x00 5241 0x00 5242 0x00 5243 0x00 5244 0x00 5245 0x00 5246 005247 0x00 5248 0x00 5249 Reserved area (6 bytes) UART2 UART2_SR UART2 status register C0h UART2_DR UART2 data register xx UART2_BRR1 UART2 baud rate register 1 0x00 UART2_BRR2 UART2 baud rate register 2 0x00 UART2_CR1 UART2 control register 1 0x00 UART2_CR2 UART2 control register 2 0x00 UART2_CR3 UART2 control register 3 0x00 UART2_CR4 Reserved UART2 control register 4 0x00 UART2_CR6 UART2 control register 6 0x00 38/127 DocID14771 Rev 9 STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 0x00 524A 0x00 524B 0x00 524C to 0x00 524F 0x00 5250 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 UART2_GTR UART2 guard time register UART2_PSCR UART2 prescaler register 0x00 Reserved area (4 bytes) TIM1 TIM1_CR1 TIM1 control register 1 0x00 TIM1_CR2 TIM1 control register 2 0x00 TIM1_SMCR TIM1 slave mode control register 0x00 TIM1_ETR TIM1 external trigger register 0x00 TIM1_IER TIM1 interrupt enable register 0x00 TIM1_SR1 TIM1 status register 1 0x00 TIM1_SR2 TIM1 status register 2 0x00 TIM1_EGR TIM1 event generation register 0x00 TIM1_CCMR1 TIM1 capture/ compare mode register 1 0x00 0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00 DocID14771 Rev 9 39/127 Memory and register map STM8S105xx Address Block Register label Register name Reset status 0x00 0x00 525A TIM1_CCMR3 TIM1 capture/ compare mode register 3 0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00 0x00 525C TIM1_CCER1 TIM1 capture/ compare enable register 1 0x00 0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0x00 0x00 525E 0x00 525F 0x00 5260 0x00 5261 0x00 5262 0x00 5263 0x00 5264 0x00 5265 0x00 5266 TIM1_CNTRH TIM1 counter high 0x00 TIM1_CNTRL TIM1 counter low 0x00 TIM1_PSCRH TIM1 prescaler register high 0x00 TIM1_PSCRL TIM1 prescaler register low 0x00 TIM1_ARRH TIM1 auto-reload register high 0xFF TIM1_ARRL TIM1 auto-reload register low 0xFF TIM1_RCR TIM1 repetition counter register 0x00 TIM1_CCR1H TIM1 capture/ compare register 1 high 0x00 TIM1_CCR1L TIM1 capture/ compare register 1 low 0x00 40/127 DocID14771 Rev 9 STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 5267 0x00 5268 0x00 5269 0x00 526A 0x00 526B 0x00 526C 0x00 526D 0x00 526E 0x00 526F 0x00 5270 to 0x00 52FF 0x00 5300 0x00 5301 0x00 5302 TIM1_CCR2H TIM1 capture/ compare register 2 high 0x00 TIM1_CCR2L TIM1 capture/ compare register 2 low 0x00 TIM1_CCR3H TIM1 capture/ compare register 3 high 0x00 TIM1_CCR3L TIM1 capture/ compare register 3 low 0x00 TIM1_CCR4H TIM1 capture/ compare register 4 high 0x00 TIM1_CCR4L TIM1 capture/ compare register 4 low 0x00 TIM1_BKR TIM1 break register 0x00 TIM1_DTR TIM1 dead-time register 0x00 TIM1_OISR TIM1 output idle state register 0x00 Reserved area (147 bytes) TIM2 TIM2_CR1 TIM2 control register 1 0x00 TIM2_IER TIM2 interrupt enable register 0x00 TIM2_SR1 TIM2 status register 1 0x00 DocID14771 Rev 9 41/127 Memory and register map STM8S105xx Address Block Register label Register name Reset status 0x00 0x00 5303 0x00 5304 0x00 5305 TIM2_SR2 TIM2 status register 2 TIM2_EGR TIM2 event generation register 0x00 TIM2_CCMR1 TIM2 capture/ compare mode register 1 0x00 0x00 5306 TIM2_CCMR2 TIM2 capture/ compare mode register 2 0x00 0x00 5307 TIM2_CCMR3 TIM2 capture/ compare mode register 3 0x00 0x00 5308 0x00 5309 0x00 530A 0x00 530B 0x00 530C 0x00 530D 0x00 530E 0x00 530F TIM2_CCER1 TIM2 capture/ compare enable register 1 TIM2 capture/ compare enable register 2 TIM2 counter high 0x00 TIM2_CCER2 0x00 TIM2_CNTRH 0x00 TIM2_CNTRL TIM2 counter low 0x00 TIM2_PSCR TIM2 prescaler register 0x00 TIM2_ARRH TIM2 auto-reload register high 0xFF TIM2_ARRL TIM2 auto-reload register low 0xFF TIM2_CCR1H TIM2 capture/ compare register 1 high 0x00 42/127 DocID14771 Rev 9 STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 5310 0x00 5311 0x00 5312 0x00 5313 0x00 5314 0x00 5315 to 0x00 531F 0x00 5320 0x00 5321 0x00 5322 0x00 5323 0x00 5324 0x00 5325 TIM2_CCR1L TIM2 capture/ compare register 1 low 0x00 TIM2_CCR2H TIM2 capture/ compare reg. 2 high 0x00 TIM2_CCR2L TIM2 capture/ compare register 2 low 0x00 TIM2_CCR3H TIM2 capture/ compare register 3 high 0x00 TIM2_CCR3L TIM2 capture/ compare register 3 low 0x00 Reserved area (11 bytes) TIM3 TIM3_CR1 TIM3 control register 1 0x00 TIM3_IER TIM3 interrupt enable register 0x00 TIM3_SR1 TIM3 status register 1 0x00 TIM3_SR2 TIM3 status register 2 0x00 TIM3_EGR TIM3 event generation register 0x00 TIM3_CCMR1 TIM3 capture/ compare mode register 1 0x00 0x00 5326 TIM3_CCMR2 TIM3 capture/ compare mode register 2 0x00 DocID14771 Rev 9 43/127 Memory and register map STM8S105xx Address Block Register label Register name Reset status 0x00 0x00 5327 0x00 5328 0x00 5329 0x00 532A 0x00 532B 0x00 532C 0x00 532D 0x00 532E 0x00 532F 0x00 5330 0x00 5331 to 0x00 533F 0x00 5340 0x00 5341 TIM3_CCER1 TIM3 capture/ compare enable register 1 TIM3 counter high TIM3_CNTRH 0x00 TIM3_CNTRL TIM3 counter low 0x00 TIM3_PSCR TIM3 prescaler register 0x00 TIM3_ARRH TIM3 auto-reload register high 0xFF TIM3_ARRL TIM3 auto-reload register low 0xFF TIM3_CCR1H TIM3 capture/ compare register 1 high 0x00 TIM3_CCR1L TIM3 capture/ compare register 1 low 0x00 TIM3_CCR2H TIM3 capture/ compare register 2 high 0x00 TIM3_CCR2L TIM3 capture/ compare register 2 low 0x00 Reserved area (15 bytes) TIM4 TIM4_CR1 TIM4 control register 1 0x00 TIM4_IER TIM4 interrupt enable register 0x00 44/127 DocID14771 Rev 9 STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 0x00 5342 0x00 5343 0x00 5344 0x00 5345 0x00 5346 0x00 5347 to 0x00 53DF 0x00 53E0 to 0x00 53F3 0x00 53F4 to 0x00 53FF 0x00 5400 0x00 5401 0x00 5402 0x00 5403 TIM4_SR TIM4 status register TIM4_EGR TIM4 event generation register 0x00 TIM4_CNTR TIM4 counter 0x00 TIM4_PSCR TIM4 prescaler register 0x00 TIM4_ARR TIM4 auto-reload register 0xFF Reserved area (153 bytes) ADC1 ADC _DBxR ADC data buffer registers 0x00 Reserved area (12 bytes) ADC1 ADC _CSR ADC control/ status register 0x00 ADC_CR1 ADC configuration register 1 0x00 ADC_CR2 ADC configuration register 2 0x00 ADC_CR3 ADC configuration register 3 0x00 DocID14771 Rev 9 45/127 Memory and register map STM8S105xx Address Block Register label Register name Reset status 0x00 0x00 5404 0x00 5405 0x00 5406 ADC_DRH ADC data register high ADC_DRL ADC data register low 0x00 ADC_TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00 0x00 5408 0x00 5409 0x00 540A 0x00 540B 0x00 540C ADC_HTRH ADC high threshold register high 0x03 ADC_HTRL ADC high threshold register low 0xFF ADC_LTRH ADC low threshold register high 0x00 ADC_LTRL ADC low threshold register low 0x00 ADC_AWSRH ADC analog watchdog status register high 0x00 0x00 540D ADC_AWSRL ADC analog watchdog status register low 0x00 0x00 540E ADC _AWCRH ADC analog watchdog control register high 0x00 0x00 540F ADC_AWCRL ADC analog watchdog control register low 0x00 0x00 5410 to Reserved area (1008 bytes) 46/127 DocID14771 Rev 9 STM8S105xx Memory and register map Address 0x00 57FF Block Register label Register name Reset status 6.2.3 CPU/SWIM/debug module/interrupt controller registers Table 10: CPU/SWIM/debug module/interrupt controller registers Address Block Register label Register name Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0xFF 0x28 0x00 7F00 CPU 0x00 7F01 0x00 7F02 0x00 7F03 0x00 7F04 0x00 7F05 0x00 7F06 0x00 7F07 0x00 7F08 0x00 7F09 0x00 7F0A 0x00 7F0B to 0x00 7F5F (1) A PCE PCH PCL XH XL YH YL SPH SPL CCR Accumulator Program counter extended Program counter high Program counter low X index register high X index register low Y index register high Y index register low Stack pointer high Stack pointer low Condition code register Reserved area (85 bytes) 0x00 7F60 CPU CFG_GCR Global configuration register 0x00 DocID14771 Rev 9 47/127 Memory and register map STM8S105xx Address Block Register label Register name Reset status 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 7F70 ITC SPR 0x00 7F71 0x00 7F72 0x00 7F73 0x00 7F74 0x00 7F75 0x00 7F76 0x00 7F77 ITC_SPR1 ITC_SPR2 ITC_SPR3 ITC_SPR4 ITC_SPR5 ITC_SPR6 ITC_SPR7 ITC_SPR8 Interrupt software priority register 1 Interrupt software priority register 2 Interrupt software priority register 3 Interrupt software priority register 4 Interrupt software priority register 5 Interrupt software priority register 6 Interrupt software priority register 7 Interrupt software priority register 8 0x00 7F78 Reserved area (2 bytes) to 0x00 7F79 0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00 0x00 7F81 Reserved area (15 bytes) to 0x00 7F8F 0x00 7F90 DM 0x00 7F91 0x00 7F92 0x00 7F93 0x00 7F94 0x00 7F95 0x00 7F96 DM_BK1RE DM_BK1RH DM_BK1RL DM_BK2RE DM_BK2RH DM_BK2RL DM_CR1 DM breakpoint 1 register extended byte DM breakpoint 1 register high byte DM breakpoint 1 register low byte DM breakpoint 2 register extended byte DM breakpoint 2 register high byte DM breakpoint 2 register low byte DM debug module control register 1 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 48/127 DocID14771 Rev 9 STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 0x10 0x00 7F97 0x00 7F98 DM_CR2 DM_CSR1 DM debug module control register 2 DM debug module control/status register 1 0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00 0x00 7F9A 0x00 7F9B to 0x00 7F9F (1) DM_ENFCTR DM enable function register 0xFF Reserved area (5 bytes) Accessible by debug module only DocID14771 Rev 9 49/127 Interrupt vector mapping STM8S105xx 7 Interrupt vector mapping Table 11: Interrupt mapping IRQ no. Source block Description Wakeup from halt mode Yes Wakeup from Vector active-halt address mode Yes Yes (1) RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 SPI TIM1 TLI AWU CLK EXTI0 EXTI1 EXTI2 EXTI3 EXTI4 Reset Software interrupt 0x00 8000 0x00 8004 0x00 8008 0x00 800C 0x00 8010 External top level interrupt Auto wake up from halt Clock controller Port A external interrupts Port B external interrupts Port C external interrupts Port D external interrupts Port E external interrupts Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes (1) 0x00 8014 0x00 8018 0x00 801C 0x00 8020 0x00 8024 0x00 8028 Reserved End of transfer TIM1 update/ overflow/ underflow/ trigger/ break TIM1 capture/ compare TIM update/ overflow TIM capture/ compare Yes - Yes - 0x00 802C 0x00 8030 0x00 8034 12 13 14 TIM1 TIM TIM - - 0x00 8038 0x00 803C 0x00 8040 50/127 DocID14771 Rev 9 STM8S105xx Interrupt vector mapping IRQ no. Source block Description Wakeup from halt mode Yes - Wakeup from Vector active-halt address mode Yes 0x00 8044 0x00 8048 0x00 804C 0x00 8050 0x00 8054 0x00 8058 0x00 805C 15 16 17 18 19 20 21 TIM3 TIM3 Update/ overflow Capture/ compare Reserved Reserved IC UART2 UART2 2 I C interrupt Tx complete Receive register DATA FULL 2 22 ADC1 ADC1 end of conversion/ analog watchdog interrupt TIM update/ overflow EOP/ WR_PG_DIS - - 0x00 8060 23 24 TIM Flash - 0x00 8064 0x00 8068 0x00 806C to 0x00 807C Reserved (1) Except PA1 DocID14771 Rev 9 51/127 Option bytes STM8S105xx 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below. Option bytes can also be modified `on the fly' by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 12: Option bytes Addr. Option name Option Option bits byte no. 7 6 5 4 3 2 1 0 Factory default setting 0x4800 Read-out protection (ROP) User boot code(UBC) OPT0 ROP [7:0] 00h 0x4801 0x4802 0x4803 0x4804 OPT1 NOPT1 UBC [7:0] NUBC [7:0] AFR7 NAFR7 AFR6 NAFR6 AFR5 NAFR5 AFR4 NAFR4 AFR3 NAFR3 AFR2 NAFR2 AFR1 NAFR1 AFR0 NAFR0 00h FFh 00h FFh Alternate function remapping (AFR) Miscell. option OPT2 NOPT2 0x4805h OPT3 Reserved HSI TRIM NHSI TRIM LSI_ EN IWDG _HW NIWDG _HW CKAWU SEL NCKA WUSEL WWDG _HW NWWDG _HW PRS C1 WWDG _HALT NWW G_HALT PRS C0 00h 0x4806 NOPT3 Reserved NLSI_ EN EXT CLK FFh 0x4807 Clock option OPT4 Reserved 00h 0x4808 NOPT4 Reserved NEXT CLK NPRSC1 NPR SC0 FFh 0x4809 0x480A 0x480B HSE clock startup OPT5 NOPT5 HSECNT [7:0] NHSECNT [7:0] Reserved 00h FFh 00h Reserved OPT6 52/127 DocID14771 Rev 9 STM8S105xx Option bytes Addr. Option name Option Option bits byte no. 7 6 5 4 3 2 1 0 Factory default setting 0x480C 0x480D 0x480E 0x487E 0x487F Bootloader Reserved NOPT6 OPT7 NOPT7 OPTBL NOPTBL Reserved Reserved Reserved BL[7:0] NBL[7:0] FFh 00h FFh 00h FFh Table 13: Option byte description Option byte no. OPT0 Description ROP[7:0] Memory readout protection (ROP) AAh: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. OPT1 UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Page 0 to 1 defined as UBC, memory write-protected 0x02: Page 0 to 3 defined as UBC, memory write-protected 0x03: Page 0 to 4 defined as UBC, memory write-protected ... 0x3E: Pages 0 to 63 defined as UBC, memory write-protected Other values: Reserved Note: Refer to the family reference manual (RM0016) section on Flash write protection for more details. OPT2 AFR[7:0] Refer to following table for the alternate function remapping decriptions of bits [7:2]. OPT3 HSITRIM:High speed internal clock trimming register size 0: 3-bit trimming supported in CLK_HSITRIMR register 1: 4-bit trimming supported in CLK_HSITRIMR register DocID14771 Rev 9 53/127 Option bytes STM8S105xx Option byte no. Description LSI_EN:Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active OPT4 EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN CKAWUSEL:Auto wake-up unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for for AWU PRSC[1:0] AWU clock prescaler 0x: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler OPT5 HSECNT[7:0]:HSE crystal oscillator stabilization time 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles 54/127 DocID14771 Rev 9 STM8S105xx Option bytes Option byte no. OPT6 OPT7 OPTBL Description Reserved Reserved BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) for more details. For STM8L products, the bootloader option bytes are on addresses 0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control whether the bootloader is active or not. For more details, refer to the UM0560 (STM8L/S bootloader manual) for more details. Table 14: Description of alternate function remapping bits [7:0] of OPT2 Option byte no. OPT2 Description (1) AFR7 Alternate function remapping option 7 0: AFR7 remapping option inactive: Default alternate function . 1: Port D4 alternate function = BEEP. AFR6 Alternate function remapping option 6 0: AFR6 remapping option inactive: Default alternate functions . 1: Port B5 alternate function = I C_SDA; port B4 alternate function 2 = I C_SCL. AFR5 Alternate function remapping option 5 0: AFR5 remapping option inactive: Default alternate functions . 1: Port B3 alternate function = TIM1_ETR; port B2 alternate function = TIM1_NCC3; port B1 alternate function = TIM1_CH2N; port B0 alternate function = TIM1_CH1N. AFR4 Alternate function remapping option 4 0: AFR4 remapping option inactive: Default alternate function . 1: Port D7 alternate function = TIM1_CH4. AFR3 Alternate function remapping option 3 0: AFR3 remapping option inactive: Default alternate function . 1: Port D0 alternate function = TIM1_BKIN. AFR2 Alternate function remapping option 2 (2) (2) (2) 2 (2) (2) DocID14771 Rev 9 55/127 Option bytes STM8S105xx Option byte no. Description (1) (2) 0: AFR2 remapping option inactive: Default alternate function . 1: Port D0 alternate function = CLK_CCO.Note: AFR2 option has priority over AFR3 if both are activated. AFR1 Alternate function remapping option 1 0: AFR1 remapping option inactive: Default alternate functions . 1: Port A3 alternate function = TIM3_CH1; port D2 alternate function TIM2_CH3. AFR0 Alternate function remapping option 0 0: AFR0 remapping option inactive: Default alternate function . 1: Port D3 alternate function = ADC_ETR. (1) (2) (2) (2) Do not use more than one remapping option in the same port. Refer to pinout description. 56/127 DocID14771 Rev 9 STM8S105xx Unique ID 9 Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: For use as serial numbers * increase the code security in * For use as security keys to ID with software cryptograhicthe program memory while using and combining this unique primitives and protocols before programming the internal memory. * To activate secure boot processes Table 15: Unique ID registers (96 bits) Address Content description 0x48CD 0x48CE 0x48CF 0x48D0 0x48D1 0x48D2 0x48D3 0x48D4 0x48D5 0x48D6 0x48D7 0x48D8 Lot number X co-ordinate on the wafer Y co-ordinate on the wafer Wafer number Unique ID bits 7 6 5 4 3 U_ID[7:0] U_ID[15:8] U_ID[23:16] U_ID[31:24] U_ID[39:32] U_ID[47:40] U_ID[55:48] U_ID[63:56] U_ID[71:64] U_ID[79:72] U_ID[87:80] U_ID[95:88] 2 1 0 DocID14771 Rev 9 57/127 Electrical characteristics STM8S105xx 10 10.1 Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 10.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 5 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ). 10.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 Typical current consumption For typical current consumption measurements, VDD, VDDIO and VDDA are connected together in the configuration shown in the following figure. Figure 8: Supply current measurement conditions 5 V or 3.3 V A V DD V DDA V DDIO V SS VSSA VSSIO 58/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics 10.1.5 Loading capacitor The loading conditions used for pin parameter measurement are shown in the following figure. Figure 9: Pin loading conditions STM8 PIN 50 pF 10.1.6 Pin input voltage The input voltage measurement on a pin of the device is described in the following figure. Figure 10: Pin input voltage STM8 PIN VIN 10.2 Absolute maximum ratings Stresses above those listed as `absolute maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 16: Voltage characteristics Symbol VDDx - VSS VIN Ratings Supply voltage (including VDDA and VDDIO) (1) Min -0.3 VSS - 0.3 Max 6.5 6.5 Unit V Input voltage on true open drain pins (PE1, (2) PE2) DocID14771 Rev 9 59/127 Electrical characteristics STM8S105xx Symbol Ratings Input voltage on any other pin (2) Min VSS - 0.3 Max VDD + 0.3 50 Unit |VDDx VDD| Variations between different power pins mV |VSSx - VSS| Variations between all the different ground pins VESD Electrostatic discharge voltage 50 see Absolute maximum ratings (electrical sensitivity) (1) All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external power supply (2) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Max. 60 60 20 20 (1) Unit mA (2) Output current sunk by any I/O and control pin Output current source by any I/Os and control pin IIO Total output current sourced (sum of all I/O and control 200 (3) pins) for devices with two VDDIO pins Total output current sourced (sum of all I/O and control 100 (3) pins) for devices with one VDDIO pin Total output current sunk (sum of all I/O and control (3) pins) for devices with two VSSIO pins Total output current sunk (sum of all I/O and control (3) pins) for devices with one VSSIO pin 160 80 60/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Symbol IINJ(PIN) (4) (5) Ratings Injected current on NRST pin Injected current on OSCIN pin Injected current on any other pin (6) Max. 4 4 4 (6) (1) Unit IINJ(PIN) (1) (2) (4) Total injected current (sum of all I/O and control pins) 20 Data based on characterization results, not tested in production. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external supply. (3) I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package between the VDDIO/VSSIO pins. (4) IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN Negative injection disturbs the analog performance of the device. See note in I2C interface characteristics. (6) When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device. Table 18: Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature Value -65 to 150 150 Unit C 10.3 Operating conditions The device must be used in operating conditions that respect the parameters in the table below. In addition, full account must be taken of all physical capacitor characteristics and tolerances. DocID14771 Rev 9 61/127 Electrical characteristics Table 19: General operating conditions Symbol fCPU Parameter Internal CPU clock frequency Standard operating voltage CEXT: capacitance of (1) external capacitor ESR of external (1) capacitor ESL of external (1) capacitor PD (2) STM8S105xx Conditions Min 0 Max 16 Unit MHz VDD/ VDD_IO 2.95 5.5 V VCAP at 1 MHz 470 3300 nF 0.3 Ohm 15 nH Power dissipation at TA = 85 C for suffix 6or TA= 125 C for suffix 3 44 and 48-pin devices, with output on eight standard ports, two high sink ports and two open drain ports (3) simultaneously 32-pin package, with output on eight standard ports and two high sink (3) ports simultaneously 443 mW 360 TA Ambient temperature for 6 suffix version Ambient temperature for 3 suffix version Maximum power dissipation Maximum power dissipation 6 suffix version 3 suffix version -40 85 C -40 125 TJ Junction temperature range -40 -40 105 130 (4) (1) Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on temperature, DC bias and frequency in addition to other factors. 62/127 DocID14771 Rev 9 STM8S105xx (2) Electrical characteristics To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/JA (see Thermal characteristics ) with the value for TJmax given in the current table and the value for JA given in Thermal characteristics. (3) (4) Refer to Thermal characteristics. TJmax is given by the test limit. Above this value the product behavior is not guaranteed. Figure 11: fCPUmax versus VDD f CPU (MHz) Functionality 16 not guaranteed in this area 12 8 4 0 2.95 4.0 5.0 5.5 Functionality guaranteed @TA-40 to 125 C Supply voltage Table 20: Operating conditions at power-up/power-down Symbol tVDD Parameter VDD rise time rate VDD fall time rate tTEMP VIT+ Reset releasedelay Power-on reset threshold Brown-out reset threshold Brown-out reset hysteresis VDD rising 2.65 2.8 Conditions Min 2 2 (1) Typ Max 1.7 (1) Unit s/V (1) ms V 2.95 VIT- 2.58 2.7 2.88 VHYS(BOR) 70 mV (1) Guaranteed by design, not tested in production. DocID14771 Rev 9 63/127 Electrical characteristics STM8S105xx 10.3.1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit the series inductance to less than 15 nH. Figure 12: External capacitor CEXT C ESL ESR RLeak 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. 10.3.2 Supply current characteristics The current consumption is measured as described in Pin input voltage. 10.3.2.1 Total current consumption in run mode Table 21: Total current consumption with code execution in run mode at VDD = 5 V Symbol Parameter Conditions HSE crystal osc. (16 MHz) HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER/128 = HSE user ext. clock 125 kHz (16 MHz) HSI RC osc. (16 MHz) 1.6 2.2 2.5 3.2 2.6 3.2 Typ Max 3.2 (1) Unit mA IDD(RUN) Supply fCPU = fMASTER current in run = 16 MHz mode, code executed from RAM 1.3 2.0 64/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Symbol Parameter Conditions fCPU = fMASTER/128 = HSI RC osc. 15.625 kHz (16 MH3z/8) fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) HSE crystal osc. (16 MHz) HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER = 2 MHz HSI RC osc. (16 MHz/8) (2) Typ Max 0.75 (1) Unit 0.55 IDD(RUN) Supply fCPU = fMASTER current in run = 16 MHz mode, code executed fromFlash 7.7 7.0 8 7.0 8.0 1.5 fCPU = fMASTER/128 = HSI RC osc. 125 kHz (16 MHz) fCPU = fMASTER/128 = HSI RC osc. 15.625 kHz (16 MHz/8) fCPU = fMASTER = 128 kHz (1) (2) 1.35 2.0 0.75 LSI RC osc. (128 kHz) 0.6 Data based on characterization results, not tested in production. Default clock configuration measured with all peripherals off. Table 22: Total current consumption with code execution in run mode at VDD = 3.3 V Symbol Parameter Conditions IDD(RUN) Supply current in run fCPU = fMASTER = 16 MHz HSE crystal osc. (16 MHz) Typ Max 2.8 (1) Unit mA DocID14771 Rev 9 65/127 Electrical characteristics STM8S105xx Symbol Parameter Conditions mode, code executed from RAM HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER/128 = 125 kHz HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER/128 = 15.625 kHz fCPU = fMASTER = 128 kHz Typ Max 2.6 3.2 (1) Unit 2.5 3.2 1.6 2.2 1.3 2.0 HSI RC osc. (16 MHz/8) 0.75 LSI RC osc. (128 kHz) 0.55 Supply fCPU = fMASTER = 16 MHz current in run mode, code executed from Flash HSE crystal osc. (16 MHz) HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz) 7.3 7.0 8 7.0 8.0 fCPU = fMASTER = 2 MHz HSI RC osc. (16 MHz/8) (2) 1.5 fCPU = fMASTER/128 = 125 kHz fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz) HSI RC osc. (16 MHz/8) 1.35 2.0 0.75 66/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Symbol Parameter Conditions fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) (1) (2) Typ Max 0.6 (1) Unit Data based on characterization results, not tested in production. Default clock configuration measured with all peripherals off. 10.3.2.2 Total current consumption in wait mode Table 23: Total current consumption in wait mode at VDD = 5 V Symbol Parameter IDD(WFI) Supply current in wait mode Conditions fCPU = fMASTER = 16 MHz HSE crystal osc. (16 MHz) HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) HSI RC osc. (16 MHz/8) (2) Typ Max 2.15 (1) Unit mA 1.55 2.0 1.5 1.9 1.3 fCPU = fMASTER/128 = 15.625 kHz 0.7 fCPU = fMASTER = 128 kHz (1) (2) LSI RC osc. (128 kHz) 0.5 Data based on characterization results, not tested in production. Default clock configuration measured with all peripherals off. DocID14771 Rev 9 67/127 Electrical characteristics STM8S105xx Table 24: Total current consumption in wait mode at VDD = 3.3 V Symbol Parameter IDD(WFI) Supply current in wait mode Conditions fCPU = fMASTER = 16 MHz HSE crystal osc. (16 MHz) HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) HSI RC osc. (16 MHz/8) (2) Typ Max 1.75 (1) Unit mA 1.55 2.0 1.5 1.9 1.3 fCPU = fMASTER/128 = 15.625 kHz 0.7 fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.5 (1) (2) Data based on characterization results, not tested in production. Default clock configuration measured with all peripherals off. 10.3.2.3 Total current consumption in active halt mode Table 25: Total current consumption in active halt mode at VDD = 5 V Symbol Parameter Conditions Main Flash mode voltage regulator (2) (MVR) IDD(AH) Supply On current in active halt mode Operating mode (3) Typ Clock source Max at 85 (1) C Max at Unit 125 (1) C HSE crystal osc. (16 MHz) LSI RC osc. 1080 A 200 320 400 68/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Symbol Parameter Conditions Main Flash mode voltage regulator (2) (MVR) (3) Typ Clock source Max at 85 (1) C Max at Unit 125 (1) C (128 kHz) Power-down mode HSE crystal osc. (16 MHz) LSI RC osc. (128 kHz) Off Operating mode Power-down mode (1) (2) (3) 1030 140 270 350 LSI RC osc. (128 kHz) 68 120 220 12 60 150 Data based on characterization results, not tested in production Configured by the REGAH bit in the CLK_ICKR register. Configured by the AHALT bit in the FLASH_CR1 register. Table 26: Total current consumption in active halt mode at VDD = 3.3 V Symbol Parameter Conditions Main Flash (3) voltage mode regulator (2) (MVR) Typ Max Max at Unit at 85 125 (1) (1) C C Clock source IDD(AH) Supply current in active halt mode On Operating mode HSE crystal osc. (16 MHz) LSI RC osc. (128 kHz) 680 A 200 320 400 DocID14771 Rev 9 69/127 Electrical characteristics STM8S105xx Symbol Parameter Conditions Main Flash (3) voltage mode regulator (2) (MVR) Typ Max Max at Unit at 85 125 (1) (1) C C Clock source Power-down HSE crystal mode osc. (16 MHz) LSI RC osc. (128 kHz) Off Operating mode Power-down mode (1) (2) (3) 630 140 270 350 LSI RC osc. (128 kHz) 66 120 220 10 60 150 Data based on characterization results, not tested in production. Configured by the REGAH bit in the CLK_ICKR register. Configured by the AHALT bit in the FLASH_CR1 register. 10.3.2.4 Total current consumption in halt mode Table 27: Total current consumption in halt mode at VDD = 5 V Symbol Parameter Conditions Typ Max at Max at Unit (1) 85 C 125 (1) C 90 150 A IDD(H) Supply current in halt mode Flash in operating mode, HSI clock after wakeup Flash in powerdown mode, HSI clock after wakeup 62 6.5 25 80 (1) Data based on characterization results, not tested in production. 70/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Table 28: Total current consumption in halt mode at VDD = 3.3 V Symbol Parameter Conditions Typ Max at Max at Unit (1) 85 C 125 (1) C 90 150 A IDD(H) Supply current in halt mode Flash in operating mode, HSI 60 clock after wakeup Flash in powerdown mode, HSI clock after wakeup 4.5 20 80 (1) Data based on characterization results, not tested in production. 10.3.2.5 Low power mode wakeup times Table 29: Wakeup times (1) Symbol Parameter Wakeup time from wait mode to run (3) mode Wakeup time active halt mode to run (3) mode Wakeup time active halt mode to run (3) mode Conditions 0 to 16 MHz fCPU = fMASTER = 16 MHz MVR voltage Flash in operating regulator (5) mode (4) on MVR voltage Flash in regulator power-down (4) (5) on mode MVR voltage Flash in operating regulator (5) mode (4) off MVR voltage Flash in regulator power-down (4) (5) off mode Flash in operating mode (5) (5) Typ Max Unit tWU(WFI) See (2) note 0.56 HSI (6) (after 1 wakeup) HSI (6) (after 3 wakeup) HSI (6) (after 48 wakeup) HSI (6) (after 50 wakeup) 52 54 2 (6) tWU(AH) s Wakeup time active halt mode to run (3) mode Wakeup time active halt mode to run (3) mode tWU(H) Wakeup time from halt mode to run (3) mode Flash in power-down mode (1) (2) (3) Data guaranteed by design, not tested in production. tWU(WFI) = 2 x 1/fmaster + 6 x 1/fCPU. Measured from interrupt event to interrupt vector fetch. DocID14771 Rev 9 71/127 Electrical characteristics (4) (5) (6) STM8S105xx Configured by the REGAH bit in the CLK_ICKR register. Configured by the AHALT bit in the FLASH_CR1 register. Plus 1 LSI clock depending on synchronization. 10.3.2.6 Total current consumption and timing in forced reset state Table 30: Total current consumption and timing in forced reset state Symbol IDD(R) Parameter Supply current in reset (2) state Conditions VDD = 5 V VDD = 3.3 V Typ 500 Max (1) Unit A 400 tRESETBL Reset pin release to vector fetch 150 s (1) (2) Data guaranteed by design, not tested in production. Characterized with all I/Os tied to VSS. 10.3.2.7 Current consumption of on-chip peripherals Subject to general operating conditions for VDD and TA. HSI internal RC/fCPU = fMASTER = 16 MHz. Table 31: Peripheral current consumption Symbol IDD(TIM1) IDD(TIM2) IDD(TIM3) IDD(TIM4) IDD(UART2) IDD(SPI) Parameter TIM1 supply current TIM2 supply current (1) Typ. 230 115 (1) Unit (1) TIM3 timer supply current TIM4 timer supply current UART2 supply current SPI supply current (2) (2) 90 A 30 110 45 (1) 72/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Symbol IDD(I 2 C) Parameter I C supply current 2 (2) Typ. 65 (3) Unit IDD(ADC1) (1) ADC1 supply current when converting 955 Data based on a differential IDD measurement between reset configuration and timer counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production. (2) Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not tested in production. (3) Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. Not tested in production. 10.3.2.8 Current consumption curves The following figures show typical current consumption measured with code executing in RAM. Figure 13: Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz DocID14771 Rev 9 73/127 Electrical characteristics STM8S105xx Figure 14: Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V Figure 15: Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz 74/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Figure 16: Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz Figure 17: Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V DocID14771 Rev 9 75/127 Electrical characteristics Figure 18: Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz STM8S105xx 10.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 32: HSE user external clock characteristics Symbol fHSE_ext VHSEH VHSEL (1) Parameter User external clock source frequency OSCIN input pin high level voltage OSCIN input pin low level voltage Conditions Min 0 0.7 x VDD VSS Max 16 VDD + 0.3 V Unit MHz (1) V 0.3 x VDD +1 A ILEAK_HSE OSCIN input leakage current (1) VSS < VIN < VDD -1 Data based on characterization results, not tested in production. 76/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Figure 19: HSE external clocksource V HSEH V HSEL External clock source fHSE OSCIN STM8 HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 33: HSE oscillator characteristics Symbol fHSE RF C (1) Parameter External high speed oscillator frequency Feedback resistor Recommended load (2) capacitance HSE oscillator power consumption Conditions Min 1 Typ Max 16 Unit MHz k 220 20 C = 20 pF, fOSC = 16 MHz C = 10 pF, fOSC =16 MHz 6 (startup) 1.6 (stabilized) 6 (startup) 1.2 (stabilized) 5 VDD is stabilized 1 (3) (3) pF IDD(HSE) mA gm tSU(HSE) (1) (2) (4) Oscillator transconductance Startup time mA/V ms C is approximately equivalent to 2 x crystal Cload. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value. Refer to crystal manufacturer for more details (3) Data based on characterization results, not tested in production. DocID14771 Rev 9 77/127 Electrical characteristics (4) STM8S105xx tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Figure 20: HSE oscillator circuit diagram Rm f HSE to core Lm Cm CO CL1 OSCIN RF gm Resonator Resonator Consumption control CL2 OSCOUT STM8 HSE oscillator critical g m equation gmcrit= (2 x x fHSE) x Rm(2Co + C) 2 2 Rm: Notional resistance (see crystal specification) Lm: Notional inductance (see crystal specification) Cm: Notional capacitance (see crystal specification) Co: Shunt capacitance (see crystal specification) CL1= CL2 = C: Grounded external capacitance gm >> gmcrit 10.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. High speed internal RC oscillator (HSI) Table 34: HSI oscillator characteristics Symbol Parameter fHSI Frequency User-trimmed with CLK_HSITRIMR register for given VDD and TA (1) conditions Conditions Min Typ 16 1.0 (2) Max Unit MHz % ACCHSI Accuracy of HSI oscillator 78/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Symbol Parameter Accuracy of HSI oscillator (factory calibrated) Conditions VDD = 5 V, TA = 25C (3) Min -1.0 -2.0 Typ Max 1.0 2.0 Unit VDD = 5 V, 25 C TA 85 C 2.95 VDD 5.5 V,-40 C TA 125 C -3.0 (3) 3.0 (3) tsu(HSI) HSI oscillator wakeup time including calibration 170 1.0 (2) s IDD(HSI) HSI oscillator power consumption (1) (2) (3) 250 (3) A Refer to application note. Guaranteed by design, not tested in production. Data based on characterization results, not tested in production. Figure 21: Typical HSI accuracy at VDD = 5 V vs 5 temperatures DocID14771 Rev 9 79/127 Electrical characteristics Figure 22: Typical HSI accuracy vs VDD @ 4 temperatures STM8S105xx Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 35: LSI oscillator characteristics Symbol fLSI tsu(LSI) IDD(LSI) (1) Parameter Frequency LSI oscillator wakeup time LSI oscillator power consumption Min 110 Typ 128 Max 146 7 (1) Unit kHz s A 5 Guaranteeed by design, not tested in production. 80/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Figure 23: Typical LSI accuracy vs VDD @ 4 temperatures 10.3.5 Memory characteristics RAM and hardware registers Table 36: RAM and hardware registers Symbol VRM (1) Parameter Data retention mode (1) Conditions Halt mode (or reset) Min VIT-max (2) Unit V Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. refer to Operating conditions for the value of VIT-max (2) Refer to the Operating conditions section for the value of VIT-max Flash program memory/data EEPROM memory General conditions: TA = -40 to 125C. Table 37: Flash program memory/data EEPROM memory Symbol Parameter VDD Operating voltage (all modes, execution/write/erase) Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) Conditions fCPU 16 MHz Min (1) Typ Max 5.5 Unit V 2.95 tprog 6 6.6 ms DocID14771 Rev 9 81/127 Electrical characteristics STM8S105xx Symbol Parameter Fast programming time for 1 block (128 bytes) terase NRW Erase time for 1 block (128 bytes) Erase/write cycles (program memory) Erase/write cycles(data memory) tRET (2) (2) Conditions Min (1) Typ Max 3 3.3 Unit ms 3 TA = +85 C 10 k 3.3 ms cycles TA = +125 C 300 k 1M 20 years Data retention (program memory) TRET = 55 C after 10k erase/write cycles at TA = +85 C Data retention (data memory) after TRET = 55 C 10k erase/write cycles at TA = +85 C Data retention (data memory) after TRET = 85 C 300 k erase/write cyclesat TA = +125 C 20 1 IDD Supply current (Flash programming or erasing for 1 to 128 bytes) 2 mA (1) (2) Data based on characterization results, not tested in production. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. 10.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 38: I/O static characteristics Symbol Parameter VIL Input low level voltage Conditions VDD = 5 V Min -0.3 Typ Max 0.3 x VDD Unit V 82/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Symbol Parameter VIH Input high level voltage Hysteresis (1) Conditions Min 0.7 x VDD Typ Max VDD + 0.3 V Unit V Vhys Rpu tR, tF 700 VDD = 5 V, VIN = VSS 30 45 60 20 (2) mV k ns ns Pull-up resistor Rise and fall Fast I/Os load = 50 pF time(10 % - 90 %) Standard and high sink I/OsLoad = 50 pF 125 (2) Ilkg Input leakage current, analog and digital Analog input leakage current VSS VIN VDD 1 (2) A Ilkg ana VSS VIN VDD 250 (2) nA Ilkg(inj) Leakage current in Injection current 4 mA (2) adjacent I/O 1 (2) A (1) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. (2) Data based on characterization results, not tested in production. Figure 24: Typical VIL and VIH vs VDD @ 4 temperatures DocID14771 Rev 9 83/127 Electrical characteristics STM8S105xx Figure 25: Typical pull-up resistance vs VDD @ 4 temperatures Figure 26: Typical pull-up current vs VDD @ 4 temperatures 1. The pull-up is a pure resistor (slope goes through 0). Table 39: Output driving current (standard ports) Symbol Parameter VOL Conditions Min Max 1 (1) Unit V Output low level with four pins IIO = 4 mA, sunk VDD = 3.3 V 84/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Symbol Parameter Output low level with eight pins sunk Conditions IIO= 10 mA, VDD = 5 V IIO = 4 mA, VDD = 3.3 V IIO = 10 mA, VDD = 5 V Min Max 2 Unit VOH Output high level with four pins sourced 2 (1) V Output high level with eight pins sourced 2.4 (1) Data based on characterization results, not tested in production Table 40: Output driving current (true open drain ports) Symbol Parameter VOL Output low level with two pins sunk Conditions IIO = 10 mA, VDD = 3.3 V IIO = 10 mA, VDD = 5 V IIO = 20 mA, VDD = 5 V Max 1.5 1 2 (1) (1) Unit V (1) Data based on characterization results, not tested in production Table 41: Output driving current (high sink ports) Symbol Parameter VOL Output low level with four pins sunk Conditions IIO = 10 mA, VDD = 3.3 V IIO = 10 mA, VDD = 5 V IIO = 20 mA, VDD = 5 V IIO = 10 mA, VDD = 3.3 V Min Max 1.1 (1) Unit V Output low level with eight pins sunk 0.9 Output low level with four pins sunk 1.6 (1) VOH Output high level with four pins sourced 1.9 (1) DocID14771 Rev 9 85/127 Electrical characteristics STM8S105xx Symbol Parameter Conditions Min 3.8 Max Unit Output high level with eight pins IIO = 10 mA, sourced VDD = 5 V Output high level with four pins sourced IIO = 20 mA, VDD = 5 V 2.9 (1) (1) Data based on characterization results, not tested in production 10.3.7 Typical output level curves The following figures show typical output level curves measured with output on a single pin. Figure 27: Typ. VOL @ VDD = 5 V (standard ports) 86/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Figure 28: Typ. VOL @ VDD = 3.3 V (standard ports) Figure 29: Typ. VOL @ VDD = 5 V (true open drain ports) DocID14771 Rev 9 87/127 Electrical characteristics Figure 30: Typ. VOL @ VDD = 3.3 V (true open drain ports) STM8S105xx Figure 31: Typ. VOL @ VDD = 5 V (high sink ports) 88/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Figure 32: Typ. VOL @ VDD = 3.3 V (high sink ports) Figure 33: Typ. VDD - VOH @ VDD = 5 V (standard ports) DocID14771 Rev 9 89/127 Electrical characteristics Figure 34: Typ. VDD - VOH @ VDD = 3.3 V (standard ports) STM8S105xx Figure 35: Typ. VDD - VOH @ VDD = 5 V (high sink ports) 90/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Figure 36: Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) 10.3.8 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 42: NRST pin characteristics Symbol VIL(NRST) VIH(NRST) VOL(NRST) RPU(NRST) tI FP(NRST) tIN FP(NRST) tOP(NRST) Parameter NRST input low (1) level voltage NRST input high (1) level voltage NRST output low (1) level voltage NRST pull-up (2) resistor NRST input filtered (3) pulse NRST input not (3) filtered pulse NRST output pulse (3) Conditions Min -0.3 V Typ Max 0.3 x VDD VDD + 0.3 0.5 Unit IOL=2 mA 0.7 x VDD V 30 40 60 75 k ns 500 s 20 (1) (2) (3) Data based on characterization results, not tested in production. The RPU pull-up equivalent resistor is based on a resistive transistor Data guaranteed by design, not tested in production. DocID14771 Rev 9 91/127 Electrical characteristics STM8S105xx Figure 37: Typical NRST VIL and VIH vs VDD @ 4 temperatures Figure 38: Typical NRST pull-up resistance vs VDD @ 4 temperatures 92/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Figure 39: Typical NRST pull-up current vs VDD @ 4 temperatures The reset network shown inthe following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in the I/O port pin characteristics section. Otherwise the reset is not taken into account internally. Figure 40: Recommended reset pin protection VDD STM8 RPU External reset circuit 0.01 F (optional) NRST Filter Internal reset 10.3.9 SPI serial peripheral interface Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). DocID14771 Rev 9 93/127 Electrical characteristics Table 43: SPI characteristics Symbol fSCK1 tc(SCK) Parameter SPI clock frequency Conditions Master mode Slave mode tr(SCK) tf(SCK) tsu(NSS) (1) STM8S105xx Min 0 0 Max 8 6 25 Unit MHz SPI clock rise and fall time Capacitive load: C = 30 pF ns NSS setup time Slave mode 4x tMASTER 70 tSCK/2 15 tSCK/2 + 15 ns th(NSS) (1) NSS hold time SCK high and low time Slave mode Master mode ns tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) (1) (1) ns (1) (1) Data input setup time Data input setup time Master mode 5 ns Slave mode 5 ns th(MI) th(SI) (1) (1) Data input hold time Data input hold time Master mode 7 ns Slave mode 10 ns ta(SO) (1) (2) Data output access time Data output disable time Data output valid time Slave mode 3x tMASTER 25 ns tdis(SO) (1) (3) Slave mode ns tv(SO) (1) Slave mode (after enable edge) Master mode (after enable edge) 73 ns tv(MO) (1) Data output valid time 36 ns 94/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Symbol th(SO) (1) Parameter Data output hold time Conditions Slave mode (after enable edge) Master mode (after enable edge) Min 28 Max Unit ns th(MO) (1) 12 ns (1) Values based on design simulation and/or characterization results, and not tested in production. (2) Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. (3) Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. Figure 41: SPI timing diagram - slave mode and CPHA = 0 NSS input tSU(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) tv(SO) MS B O UT tsu(SI) tr(SCK) tf(SCK) LSB OUT ta(SO) MISO OUT P UT MOSI I NPUT th(SO) BI T6 OUT tdis(SO) M SB IN th(SI) B I T1 IN LSB IN ai14134 DocID14771 Rev 9 95/127 Electrical characteristics Figure 42: SPI timing diagram - slave mode and CPHA = 1 STM8S105xx (1) NSS input tSU(NSS) SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN tv(SO) MS B O UT th(SI) th(SO) BI T6 OUT tdis(SO) LSB OUT B I T1 IN LSB IN ai14135 1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 43: SPI timing diagram - master mode High NSS input tc(SCK) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 (1) SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO) ai14136 tr(SCK) tf(SCK) BI T6 IN LSB IN LSB OUT 1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. 96/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics 10.3.10 I C interface characteristics Table 44: I C characteristics 2 2 Symbol Parameter Standard mode I C Min (2) 2 Fast mode I C Min 1.3 0.6 100 0 (4) (2) 2 (1) Unit Max (2) Max (2) tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) SCL clock low time SCL clock high time SDA setup time SDA data hold time 4.7 4.0 250 0 (3) s s ns 900 (3) ns SDA and SCL rise time 1000 300 ns SDA and SCL fall time 300 300 ns START condition hold time Repeated START condition setup time 4.0 0.6 s 4.7 0.6 s tsu(STO) STOP condition setup time 4.0 0.6 s tw(STO:STA) STOP to START condition time (bus free) Cb (1) (2) (3) 4.7 1.3 s Capacitive load for each bus line 2 400 400 pF fMASTER, must be at least 8 MHz to achieve max fast I C speed (400kHz). Data based on standard I C protocol requirement, not tested in production. 2 The maximum hold time of the start condition has only to be met if the interface does not stretch the low time. (4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. DocID14771 Rev 9 97/127 Electrical characteristics 2 STM8S105xx (1) Figure 44: Typical application with I C bus and timing diagram VDD VDD STM8S105xx SDA IC bus SCL S TART REPEATED S TART tsu(STA) SDA tf(SDA) th(STA) SCL tw(SCKH) S TART tr(SDA) tw(SCKL) tsu(SDA) th(SDA) S TOP tsu(STA:STO) tr(SCK) tf(SCK) tsu(STO) ai15385 1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD 10.3.11 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 45: ADC characteristics Symbol Parameter fADC ADC clock frequency Conditions Min Typ Max 4 6 5.5 (1) Unit MHz VDDA =2.95 to 5.5 V 1 VDDA =4.5 to 5.5 V 1 3 2.75 VDDA VREF+ VREFVAIN Analog supply Positive reference voltage Negative reference voltage Conversion voltage range (2) V V V V VDDA 0.5 (1) V SSA V SSA V DDA Devices with external VREF+/VREF- pins CADC Internal sample and hold capacitor VREF- VREF+ V 3 pF 98/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Symbol Parameter tS (2) Conditions fADC = 4 MHz fADC = 6 MHz Min 0.75 0.5 Typ Max Unit s Sampling time tSTAB tCONV Wakeup time from standby Total conversion time (including sampling time, 10-bit resolution) fADC = 4 MHz fADC = 6 MHz 3.5 2.33 14 7 s s s 1/fADC (1) (2) Data guaranteed by design, not tested in production.. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. Table 46: ADC accuracy with RAIN < 10 k , VDDA= 5 V Symbol |ET| Parameter Total unadjusted error (2) Conditions fADC = 2 MHz fADC = 4 MHz fADC = 6 MHz Typ 1 1.4 1.6 0.6 1.1 1.2 0.2 0.6 Max 2.5 3 3.5 2 2.5 2.5 2 2.5 (1) Unit LSB |EO| Offset error (2) fADC = 2 MHz fADC = 4 MHz fADC = 6 MHz |EG| Gain error (2) fADC = 2 MHz fADC = 4 MHz DocID14771 Rev 9 99/127 Electrical characteristics STM8S105xx Symbol Parameter Conditions fADC = 6 MHz Typ 0.8 0.7 0.7 0.8 0.6 0.6 0.6 Max 2.5 1.5 1.5 1.5 1.5 1.5 1.5 (1) Unit |ED| Differential linearity error (2) fADC = 2 MHz fADC = 4 MHz fADC = 6 MHz |EL| Integral linearity error (2) fADC = 2 MHz fADC = 4 MHz fADC = 6 MHz (1) Data based on characterisation results for LQFP80 device with VREF+/VREF-, not tested in production. (2) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy. Table 47: ADC accuracy with RAIN < 10 k RAIN, VDDA = 3.3 V Symbol |ET| Parameter Total unadjusted error (2) Conditions fADC = 2 MHz fADC = 4 MHz Typ 1.1 1.6 0.7 1.3 0.2 0.5 0.7 Max 2 2.5 1.5 2 1.5 2 1 (1) Unit LSB |EO| Offset error (2) fADC = 2 MHz fADC = 4 MHz |EG| Gain error (2) fADC = 2 MHz fADC = 4 MHz |ED| Differential linearity error (2) fADC = 2 MHz 100/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics Symbol Parameter Conditions fADC = 4 MHz Typ 0.7 0.6 0.6 Max 1 1.5 1.5 (1) Unit |EL| Integral linearity error (2) fADC = 2 MHz fADC = 4 MHz (1) Data based on characterisation results for LQFP80 device with VREF+/VREF-, not tested in production. (2) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in I/O port pin characteristics does not affect the ADC accuracy. Figure 45: ADC accuracy characteristics 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = Offset error: deviation between the first actual transition and the first ideal one. EG = Gain error: deviation between the last ideal transition and the last actual one. ED = Differential linearity error: maximum deviation between actual steps and the ideal one. DocID14771 Rev 9 101/127 Electrical characteristics STM8S105xx EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation line. Figure 46: Typical application with ADC VDD VT 0.6 V 10-bit A/D conversion VT 0.6 V IL 1 A CADC STM8 VAIN RAIN AINx CAIN 10.3.12 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 10.3.12.1 Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard. * fast transient voltage (positive and negative) is applied to and V * FTB: A burst ofpF capacitor, until a functional disturbance occurs. This testVconforms with through a 100 DD SS the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 (EMC design guide for STMicrocontrollers). 10.3.12.2 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques for improving microcontroller EMC performance). 102/127 DocID14771 Rev 9 STM8S105xx Table 48: EMS data Symbol Parameter VFESD Conditions Electrical characteristics Level/ class Voltage limits to be applied on any I/O pin to VDD = 3.3 V, TA = 25 C, fMASTER = 16 MHz (1) 2/B induce a functional (HSI clock), conforming to IEC 61000-4-2 disturbance Fast transient voltage burst limits to be applied (1) through 100 pF on VDD VDD= 3.3 V, TA = 25 C ,fMASTER = 16 MHz 4/A (HSI clock),conforming to IEC 61000-4-4 and VSS pins to induce a functional disturbance VEFTB (1) Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers). 10.3.12.3 Electromagnetic interference (EMI) Emission tests conform to the IEC61967-2 standard for test software, board layout and pin loading. Table 49: EMI data Symbol Parameter Conditions General conditions Monitored frequency band Max fHSE/fCPU 8 MHz/ 8 MHz 13 (1) Unit 8 MHz/ 16 MHz 14 dBV SEMI Peak level VDD = 5 V, TA = +25 C, LQFP48 package conforming to IEC61967-2 0.1 MHz to 30 MHz 30 MHz to 130 MHz 23 19 130 MHz to 1 -4 GHz SAE EMI level (1) -4 2 1.5 -- Data based on characterization results, not tested in production. DocID14771 Rev 9 103/127 Electrical characteristics STM8S105xx 10.3.12.4 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. 10.3.12.5 Electrostatic discharge (ESD) Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181. Table 50: ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum Unit (1) value A 2000 V VESD(HBM) Electrostatic discharge TA = +25C, voltage (Human body model) conforming to JESD22-A114 VESD(CDM) Electrostatic discharge voltage (Charge device model) (1) TA=+25C, conforming IV to JESD22-C101 1000 V Data based on characterization results, not tested in production 10.3.12.6 Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance: A supply overvoltage (applied to each power supply pin) * injection * A currentsample. (applied to each input, output and configurable I/O pin) are performed on each This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 51: Electrical sensitivities Symbol LU Parameter Static latch-up class Conditions TA = +25 C TA = +85 C TA = +125 C Class A A A (1) 104/127 DocID14771 Rev 9 STM8S105xx Electrical characteristics (1) Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). DocID14771 Rev 9 105/127 Package characteristics STM8S105xx 11 11.1 Package characteristics Ecopack packages To meet environmental requirements, ST offers these devices in different grades of ECOPACK (R) packages, depending on their level of environmental compliance. ECOPACK specifications, (R) grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark. (R) 11.2 11.2.1 Package mechanical data 48-pin LQFP package mechanical data Figure 47: 48-pin low profile quad flat package (7 x 7) D D1 D3 36 37 b E3 E1 E 25 24 L1 ccc C A A2 48 Pin 1 identification 13 1 12 A1 L K c 5B_ME Table 52: 48-pin low profile quad flat package mechanical data Dim. mm Min A A1 A2 b 0.050 1.350 0.170 1.400 0.220 Typ Max 1.600 0.150 1.450 0.270 0.0020 0.0531 0.0067 0.0551 0.0087 inches Min (1) Typ Max 0.0630 0.0059 0.0571 0.0106 106/127 DocID14771 Rev 9 STM8S105xx Package characteristics Dim. mm Min Typ Max 0.200 9.000 7.000 5.500 8.800 6.800 9.000 7.000 5.500 0.500 0.450 0.600 1.000 0.0 3.5 7.0 0.080 0.750 9.200 7.200 9.200 7.200 inches Min (1) Typ Max 0.0079 c D D1 D3 E E1 E3 e L L1 k ccc (1) 0.090 8.800 6.800 0.0035 0.3465 0.2677 0.3543 0.2756 0.2165 0.3465 0.2677 0.3543 0.2756 0.2165 0.0197 0.0177 0.0236 0.0394 0.0 3.5 0.3622 0.2835 0.3622 0.2835 0.0295 7.0 0.0031 Values in inches are converted from mm and rounded to 4 decimal digits DocID14771 Rev 9 107/127 Package characteristics STM8S105xx 11.2.2 44-pin LQFP package mechanical data Figure 48: 44-pin low profile quad flat package D D1 D3 33 34 b E3 E1 E 23 22 L1 ccc C A A2 44 Pin 1 identification 12 1 11 A1 L K c 4Y_ME Table 53: 44-pin low profile quad flat package mechanical data Dim. mm Min A A1 A2 b c D D1 D3 E 11.800 0.050 1.350 0.300 0.090 11.800 9.800 12.000 10.000 8.000 12.000 12.200 0.4646 1.400 0.370 Typ Max 1.600 0.150 1.450 0.450 0.200 12.200 10.200 0.0020 0.0531 0.0118 0.0035 0.4646 0.3858 0.4724 0.3937 0.3150 0.4724 0.4803 0.0551 0.0146 inches Min (1) Typ Max 0.0630 0.0059 0.0571 0.0177 0.0079 0.4803 0.4016 108/127 DocID14771 Rev 9 STM8S105xx Package characteristics Dim. mm Min Typ 10.000 8.000 0.800 0.450 0.600 1.000 0.0 3.5 7.0 0.100 0.750 Max 10.200 inches Min (1) Typ 0.3937 0.3150 0.0315 Max 0.4016 E1 E3 e L L1 k ccc (1) 9.800 0.3858 0.0177 0.0236 0.0394 0.0295 0.0 3.5 7.0 0.0039 Values in inches are converted from mm and rounded to 4 decimal digits 11.2.3 32-pin LQFP package mechanical data Figure 49: 32-pin low profile quad flat package (7 x 7) ccc C D D1 D3 24 25 b E3 32 Pin 1 identification E1 E 17 16 L1 A A2 9 A1 1 8 L K c 5V_ME DocID14771 Rev 9 109/127 Package characteristics STM8S105xx Table 54: 32-pin low profile quad flat package mechanical data Dim. mm Min A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc (1) inches Typ Max 1.600 Min (1) Typ Max 0.0630 0.050 1.350 0.300 0.090 8.800 6.800 9.000 7.000 5.600 8.800 6.800 9.000 7.000 5.600 0.800 0.450 0.600 1.000 0.0 3.5 1.400 0.370 0.150 1.450 0.450 0.200 9.200 7.200 0.0020 0.0531 0.0118 0.0035 0.3465 0.2677 0.3543 0.2756 0.2205 0.0551 0.0146 0.0059 0.0571 0.0177 0.0079 0.3622 0.2835 9.200 7.200 0.3465 0.2677 0.3543 0.2756 0.2205 0.0315 0.3622 0.2835 0.750 0.0177 0.0236 0.0394 0.0295 7.0 0.100 0.0 3.5 7.0 0.0039 Values in inches are converted from mm and rounded to 4 decimal digits 110/127 DocID14771 Rev 9 STM8S105xx Package characteristics 11.2.4 32-lead VFQFPN package mechanical data Figure 50: 32-lead very thin fine pitch quad flat no-lead package (5 x 5) Seating plane C A ddd C A3 A1 D e 9 8 16 17 E2 b E 1 32 24 L Pin # 1 ID R = 0.30 D2 Bottom view L 42_ME Note: 1. The exposed pad must be soldered to the PCB. It is recommended to connect it to VSS. Table 55: 32-lead very thin fine pitch quad flat no-lead package mechanical data Dim. mm Min A A1 A3 b D 0.18 4.85 0.80 0 Typ 0.90 0.02 0.20 0.25 5.00 0.30 5.15 0.0071 0.1909 Max 1.00 0.05 inches Min 0.0315 (1) Typ 0.0354 0.0008 0.0079 0.0098 0.1969 Max 0.0394 0.0020 0.0118 0.2028 DocID14771 Rev 9 111/127 Package characteristics STM8S105xx Dim. mm Min Typ 3.45 5.00 3.45 0.50 0.30 0.40 0.50 0.08 Max 3.70 5.15 3.70 inches Min (1) Typ Max 0.1457 D2 E E2 e L ddd (1) 3.20 4.85 3.20 0.1260 0.1909 0.1260 0.1969 0.1358 0.0197 0.0118 0.0157 0.2028 0.1457 0.0197 0.0031 Values in inches are converted from mm and rounded to 4 decimal digits. 11.2.5 32-lead UFQFPN package mechanical data Figure 51: 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5) AOB8_ME 112/127 DocID14771 Rev 9 STM8S105xx Package characteristics Table 56: 32-lead ultra thin fine pitch quad flat no-lead package mechanical data Dim. mm Min Typ 0.55 0.02 0.20 0.18 4.85 3.20 4.85 3.20 0.25 5.00 3.45 5.00 3.45 0.50 0.30 0.40 0.50 0.08 0.30 5.15 3.70 5.15 3.70 Max 0.6 0.05 inches Min (1) Typ 0.0217 0.0008 0.0079 Max 0.0236 0.0020 A A1 A3 b D D2 E E2 e L ddd (1) 0.50 0 0.0197 0 0.0071 0.1909 0.1260 0.1909 0.1260 0.0098 0.1969 0.1358 0.1969 0.1358 0.0197 0.0118 0.2028 0.1457 0.2028 0.1457 0.0118 0.0157 0.0197 0.0031 Values in inches are converted from mm and rounded to 4 decimal digits. DocID14771 Rev 9 113/127 Package characteristics STM8S105xx 11.2.6 SDIP32 package mechanical data Figure 52: 32-lead shrink plastic DIP (400 ml) package E E1 A2 A1 B1 B e C eA eB D A L 32 17 1 16 76_ME Table 57: 32-lead shrink plastic DIP (400 ml) package mechanical data Dim. mm Min A A1 A2 B B1 C D E E1 3.556 0.508 3.048 0.356 0.762 0.203 27.430 9.906 7.620 3.556 0.457 1.016 0.254 27.940 10.410 8.890 4.572 0.584 1.397 0.356 28.450 11.050 9.398 Typ 3.759 Max 5.080 inches Min 0.1400 0.0200 0.1200 0.0140 0.0300 0.0079 1.0799 0.3900 0.3000 0.1400 0.0180 0.0400 0.0100 1.1000 0.4098 0.3500 0.1800 0.0230 0.0550 0.0140 1.1201 0.4350 0.3700 (1) Typ 0.1480 Max 0.2000 114/127 DocID14771 Rev 9 STM8S105xx Package characteristics Dim. mm Min Typ 1.778 10.160 12.700 2.540 3.048 3.810 Max inches Min (1) Typ 0.0700 0.4000 Max e eA eB L (1) 0.5000 0.1000 0.1200 0.1500 Values in inches are converted from mm and rounded to 4 decimal digits 11.3 Thermal characteristics The maximum chip junction temperature (TJ max) must never exceed the values given in Operating conditions The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x JA) Where: TAmax is the maximum ambient temperature in C JA * * is the package junction-to-ambient thermal resistance in C/W * P is the sum of P and P (P = P + P ) * P is the product of I andV , expressed in Watts. This is the maximum chip internal power. maximum power dissipation = *I * P ((V represents thetaking into account the actualon output pinsWhere:P the I/Os(V low ) + -V *I ), V /I V /I of at Dmax INTmax DD I/Omax Dmax INTmax I/Omax INTmax DD I/Omax I/Omax OL OL DD OH) OH OL OL and OH OH and high level in the application. Table 58: Thermal characteristics Symbol JA Parameter Thermal resistance junction-ambient LQFP 48 - 7 x 7 mm JA Thermal resistance junction-ambient LQFP 44 - 10 x 10 mm 54 C/W (1) Value 57 Unit C/W DocID14771 Rev 9 115/127 Package characteristics STM8S105xx Symbol JA Parameter Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm Value 60 Unit C/W JA Thermal resistance junction-ambient VQFPN 32 - 5 x 5 mm 22 C/W 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 11.3.1 Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. 11.3.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code. The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: Maximum ambient temperature TAmaz = 82 C (measured according to JESD51-2) DDmax DD * * I = 15 mA, V = 5.5 V * Maximum 8 standard I/Os used at the same time in output at low level with I = 10 mA, V =2V * MaximumV4 high sink I/Os used at the same time in output at low level with I = 20 mA, V = 1.5 * Maximum 2=trueVopen drain I/Os used at the same time in output at low level with I = 20 mA, V 2 OL OL OL OL OL OL PINTmax = 15 mA x 5.5 V = 82.5 mW PIOmax = (10 mA x 2 V x 8 )+(20 mA x 2 V x 2)+(20 mA x 1.5 V x 4) = 360 mW This gives: PINTmax = 82.5 mW and PIOmax 360 mW: PDmax = 82.5 mW + 360 mW Thus: PDmax = 443 mW TJmax for LQFP32 can be calculated as follows, using the thermal resistance JA : TJmax = 75 C + (59 C/W x 464 mW) = 75C + 27C = 102 C This is within the range of the suffix 6 version parts (-40 < TJ < 106 C). In this case, parts must be ordered at least with the temperature range suffix 6. 116/127 DocID14771 Rev 9 STM8S105xx Ordering information 12 Ordering information Figure 53: STM8S105xx access line ordering information scheme Example: STM8 S 105 K 4 T 6 C TR Product class Family type S = Standard Sub-family type 105 = access line STM8S105x Pin count K = 32 pins S = 44 pins C = 48 pins Program memory size 4 = 16 Kbytes 6 = 32 Kbytes Package type B = SDIP T = LQFP U = VQFPN Temperature range 3 = -40 C to 125 C 6 = -40 C to 85 C Package pitch No character = 0.5 mm C = 0.8 mm Packing No character = Tray or tube TR = Tape and reel 1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST sales office nearest to you. 12.1 STM8S105 FASTROM microcontroller option list (last update: March 2010) Customer Address ............................................................................................. ............................................................................................. DocID14771 Rev 9 117/127 Ordering information STM8S105xx Contact Phone no. a ............................................................................................. ............................................................................................. Reference FASTROM code ............................................................................................. Preferable format for programing code is .Hex (.s19 is accepted) If data EEPROM programing is required, a seperate file must be sent with the requested data. Important: See the option byte section in the datasheet for authorized option byte combinations and a detailed explanation. Device type/memory size/package (check only one option) FASTROM device VFQFPN32 LQFP32 LQFP44 LQFP48 16 Kbyte [ ] STM8S105K4 [ ] STM8S105K4 [ ] STM8S105S4 [ ] STM8S105C4 32 Kbyte [ ] STM8S105K6 [ ] STM8S105K6 [ ] STM8S105S6 [ ] STM8S105C6 Conditioning (check only one option) [ ] Tape & reel or [ ] Tray Special marking (check only one option) [ ] No [ ] Yes Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character counts are: VFQFPN32: 1 line of 7 characters max: "_ _ _ _ _ _ _" LQFP32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" LQFP44: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" LQFP48: 2 lines of 8 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" Temperature range [ ] -40C to +85C or [ ] -40C to +125C Padding value for unused program memory (check only one option) [ ]0xFF [ ]0x83 [ ]0x75 Fixed value TRAP instruction opcode Illegal opcode (causes a reset when executed) OPT0 memory readout protection (check only one option) [ ] Disable or [ ] Enable OPT1 user boot code area (UBC) 0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below. a FASTROM code name is assigned by STMicroelectronics. 118/127 DocID14771 Rev 9 STM8S105xx Ordering information UBC, bit0 [ ] 0: Reset [ ] 1: Set UBC bit1 [ ] 0: Reset [ ] 1: Set UBC bit2 [ ] 0: Reset [ ] 1: Set UBC bit3 [ ] 0: Reset [ ] 1: Set UBC bit4 [ ] 0: Reset [ ] 1: Set UBC bit5 [ ] 0: Reset [ ] 1: Set UBC bit6 [ ] 0: Reset [ ] 1: Set UBC bit7 [ ] 0: Reset [ ] 1: Set OPT2 alternate function remapping AFR0 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port D3 alternate function = ADC_ETR AFR1 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port A3 alternate function = TIM3_CH1, port D2 alternate function = TIM2_CH3. AFR2 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port D0 alternate function = CLK_CCO. Note: If both AFR2 and AFR3 are activated, AFR2 option has priority over AFR3. AFR3 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. DocID14771 Rev 9 119/127 Ordering information STM8S105xx [ ] 1: Port D0 alternate function = TIM1_BKIN. AFR4 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port D7 alternate function = TIM1_CH4. AFR5 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate function = TIM1_NCC3, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N. AFR6 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate function = I2C_SCL. AFR7 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port D4 alternate function = BEEP. OPT3 watchdog WWDG_HALT (check only one option) WWDG_HW (check only one option) IWDG_HW (check only one option) LSI_EN (check only one option) HSITRIM (check only one option) [ ] 0: No reset generated on halt if WWDG active. [ ] 1: Reset generated on halt if WWDG active. [ ] 0: WWDG activated by software. [ ] 1: WWDG activated by hardware. [ ] 0: IWDG activated by software. [ ] 1: IWDG activated by hardware. [ ] 0: LSI clock is not available as CPU clock source. [ ] 1: LSI clock is available as CPU clock source. [ ] 0: 3-bit trimming supported in CLK_HSITRIMR register. [ ] 1: 4-bit trimming supported in CLK_HSITRIMR register. OPT4 wakeup PRSC (check only one option) [ ] for 16 MHz to 128 kHz prescaler. [ ] for 8 MHz to 128 kHz prescaler. [ ] for 4 MHz to 128 kHz prescaler. 120/127 DocID14771 Rev 9 STM8S105xx Ordering information CKAWUSEL (check only one option) [ ] 0: LSI clock source selected for AWU. [ ] 1: HSE clock with prescaler selected as clock source for AWU. [ ] 0: External crystal connected to OSCIN/OSCOUT. [ ] 1: External clock signal on OSCIN. EXTCLK (check only one option) OPT5 crystal oscillator stabilization HSECNT (check only one option) [ ] 2048 HSE cycles [ ] 128 HSE cycles [ ] 8 HSE cycles [ ] 0.5 HSE cycles OPT6 is reserved OPT7 is reserved OPTBL bootloader option byte (check only one option) Refer to the UM0560 (STM8L/S bootloader manual) for more details. [ ] 00h [ ] 55h Comments: ........................................................................................................... Supply operating range ........................................................................................................... in the application: Notes: Date: Signature: ........................................................................................................... ........................................................................................................... ........................................................................................................... DocID14771 Rev 9 121/127 STM8 development tools STM8S105xx 13 STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 13.1 Emulation and in-circuit debugging tools The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers. STice key features Occurrence and time profiling and code coverage (new features) * * Advanced breakpoints with up to 4 levels of conditions * Data breakpoints * Program and data trace recording up to 128 KB records * Read/write on the fly of memory during emulation * In-circuit debugging/programming via SWIM protocol * 8-bit probe analyzer * 1 input and 2 output triggers * Power supply follower managing application voltages between 1.62 to 5.5 V allows you * Modularity thatand adapt toto specify the components you need to meet your development requirements future requirements free software tools that include integrated development environment (IDE), * Supported by software interface and assembler for STM8. programming 13.2 Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs up to 16 Kbytes of code. 122/127 DocID14771 Rev 9 STM8S105xx STM8 development tools 13.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop - Full-featured integrated development environment from ST, featuring Seamless integration of C and ASM toolsets * * Full-featured debugger * Project management * Syntax highlighting editor * Integrated programming interface * Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer (STVP) - Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller's Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences. 13.2.2 C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. Available toolchains include: Cosmic C compiler for STM8 - Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.cosmic-software.com. * C compiler for STM8 - Available in a free version that * Raisonance code. For more information, see www.raisonance.com. outputs up to 16 Kbytes of - assembly toolchain included * STM8 assembler linkerandFree your application source code.in the STVD toolset, which allows you to assemble link 13.3 Programming tools During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family. DocID14771 Rev 9 123/127 Revision history STM8S105xx 14 Revision history Table 59: Document revision history Date 05-Jun-2008 23-Jun-2008 Revision 1 2 Changes Initial release. Corrected number of high sink outputs to 9 in I/Os on Features. Updated part numbers in Table 2: STM8S105xx access line features. 12-Aug-2008 3 Updated part numbers in Table 2: STM8S105xx access line features. USART renamed UART1, LINUART renamed UART2. Added Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin access line devices. 17-Sep-2008 4 Removed STM8S102xx and STM8S104xx root part numbers corresponding to devices without data EEPROM. Updated STM8S103 pinout in Section 5.2 on page 29. Added low and medium density Flash memory categories. Added Note 1 in Table 17: Current characteristics. Updated Table 12: Option bytes . 05-Feb-2009 5 Updated STM8S103 pinout in Section 5.2 on page 29 Updated number of High Sink I/Os in pinout. TSSOP20 pinout modified (PD4 moved to pin 1 etc.) Added WFQFN20 package Updated Option bytes. Added Memory and register map. 27-Feb-2009 6 Removed STM8S103x products (separate STM8S103 datasheet created) Updated Electrical characteristics. 12-May-2009 7 Added SDIP32 silhouette and package to Features and SDIP32 package mechanical data data ; updated Pinout and pin description and Updated VDD range (2.95 V to 5.5 V) on Features. 124/127 DocID14771 Rev 9 STM8S105xx Revision history Date Revision Changes Amended name of package VQFPN32 Added Table 5 on page 22 . Updated Auto wakeup counter. Updated pins 25, 30, and 31 in Pinout and pin description. Removed Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin access line devices. Added Table 14: Description of alternate function remapping bits [7:0] of OPT2. Electrical characteristics: Updated VCAP specifications; updated Table 15, Table 18, Table 20, Table 21, Table 22, Table 23, Table 24, Table 25, Table 26, Table 27, Table 29, Table 35, and Table 42; added current consumption curves ; removed Figure 20: typical HSE frequency vs fcpu @ 4 temperatures; updated Figure 13, Figure 14, Figure 15, Figure 16 and Figure 17 ; modified HSI accuracy in Table 33 ; added Figure 44 ; modified fSCK, tV(SO) and tV(MO) in Table 42 ; updated figures and tables of High speed internal RC oscillator (HSI) ; replaced Figure 23, Figure 24, Figure 26, and Figure 39 . Package characteristics: Updated Table 58: Thermal characteristics(1) and removed Table 57: Junction temperature range. Updated Figure 53: STM8S105xx access line ordering information scheme. 10-Jun-2009 8 Document status changed from "preliminary data" to "datasheet". Standardized name of the VFQFPN package. Removed `wpu' from I2C pins in Pinout and pin description 21-Apr-2010 9 Added UFQFPN32 package silhouette to the title page. Features: added unique ID. Clock controller: updated bit positions for TIM2 and TIM3. Beeper: added information about availability of the beeper output port through option bit AFR7. Analog-to-digital converter (ADC1): added a note concerning additional AIN12 analog input. STM8S105 pinouts and pin description: added UFQFPN32 package details; updated default alternate function of PB2/AIN2[TIM1_CH3N] pin in the "pin description for STM8S105 microcontrollers" table. DocID14771 Rev 9 125/127 Revision history STM8S105xx Date Revision Changes Option bytes: added description of STM8L bootloader option bytes to the option byte description table. Added Unique ID Operating conditions: added introductory text; removed low power dissipation condition for TA, replaced "CEXT" by "VCAP", and added ESR and ESL data in table "general operating conditions". Total current consumption in halt mode: replaced max value of IDD(H) at 85 C from 20 A to 25 A for the condition "Flash in powerdown mode, HSI clock after wakeup in the table "total current consumption in halt mode at VDD = 5 V. Low power mode wakeup times: added first condition (0 to 16 MHz) for the tWU(WFI) parameter in the table "wakeup times". Internal clock sources and timing characteristics: In the table "HSI oscillator characteristics", replaced min and max values of "ACCHSI factory calibrated parameter" and removed footnote 4 concerning further characterization of results. Functional EMS (electromagnetic susceptibility): IEC 1000 replaced with IEC 61000. Designing hardened software to avoid noise problems: IEC 1000 replaced with IEC 61000. Electromagnetic interference (EMI): SAE J 1752/3 replaced with IEC61967-2. Thermal characteristics: Replaced the thermal resistance junction ambient temperature of LQFP32 7X7 mm from 59 C to 60 C in the thermal characteristics table. Added 32-lead UFQFPN package mechanical data. Added STM8S105 FASTROM microcontroller option list. 126/127 DocID14771 Rev 9 STM8S105xx Please Read Carefully Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at anytime, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVEGRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately voidany warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom United States of America www.st.com DocID14771 Rev 9 127/127 |
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